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68#include <common.h>
69#include <bootretry.h>
70#include <cli.h>
71#include <command.h>
72#include <dm.h>
73#include <edid.h>
74#include <environment.h>
75#include <errno.h>
76#include <i2c.h>
77#include <malloc.h>
78#include <asm/byteorder.h>
79#include <linux/compiler.h>
80
81DECLARE_GLOBAL_DATA_PTR;
82
83
84
85
86static uint i2c_dp_last_chip;
87static uint i2c_dp_last_addr;
88static uint i2c_dp_last_alen;
89static uint i2c_dp_last_length = 0x10;
90
91static uint i2c_mm_last_chip;
92static uint i2c_mm_last_addr;
93static uint i2c_mm_last_alen;
94
95
96
97
98
99
100#if defined(CONFIG_SYS_I2C_NOPROBES)
101#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
102static struct
103{
104 uchar bus;
105 uchar addr;
106} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
107#define GET_BUS_NUM i2c_get_bus_num()
108#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
109#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
110#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
111#else
112static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
113#define GET_BUS_NUM 0
114#define COMPARE_BUS(b,i) ((b) == 0)
115#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
116#define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
117#endif
118#endif
119
120#define DISP_LINE_LEN 16
121
122
123
124
125
126
127#ifdef CONFIG_DM_I2C
128#define DEFAULT_ADDR_LEN (-1)
129#else
130#define DEFAULT_ADDR_LEN 1
131#endif
132
133#ifdef CONFIG_DM_I2C
134static struct udevice *i2c_cur_bus;
135
136static int cmd_i2c_set_bus_num(unsigned int busnum)
137{
138 struct udevice *bus;
139 int ret;
140
141 ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus);
142 if (ret) {
143 debug("%s: No bus %d\n", __func__, busnum);
144 return ret;
145 }
146 i2c_cur_bus = bus;
147
148 return 0;
149}
150
151static int i2c_get_cur_bus(struct udevice **busp)
152{
153 if (!i2c_cur_bus) {
154 puts("No I2C bus selected\n");
155 return -ENODEV;
156 }
157 *busp = i2c_cur_bus;
158
159 return 0;
160}
161
162static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp)
163{
164 struct udevice *bus;
165 int ret;
166
167 ret = i2c_get_cur_bus(&bus);
168 if (ret)
169 return ret;
170
171 return i2c_get_chip(bus, chip_addr, 1, devp);
172}
173
174#endif
175
176
177
178
179
180
181
182
183__weak
184void i2c_init_board(void)
185{
186}
187
188
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197
198
199
200
201
202#if !defined(CONFIG_SYS_I2C) && !defined(CONFIG_DM_I2C)
203
204
205
206
207__weak
208unsigned int i2c_get_bus_speed(void)
209{
210 return CONFIG_SYS_I2C_SPEED;
211}
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226__weak
227int i2c_set_bus_speed(unsigned int speed)
228{
229 if (speed != CONFIG_SYS_I2C_SPEED)
230 return -1;
231
232 return 0;
233}
234#endif
235
236
237
238
239
240
241static uint get_alen(char *arg, int default_len)
242{
243 int j;
244 int alen;
245
246 alen = default_len;
247 for (j = 0; j < 8; j++) {
248 if (arg[j] == '.') {
249 alen = arg[j+1] - '0';
250 break;
251 } else if (arg[j] == '\0')
252 break;
253 }
254 return alen;
255}
256
257enum i2c_err_op {
258 I2C_ERR_READ,
259 I2C_ERR_WRITE,
260};
261
262static int i2c_report_err(int ret, enum i2c_err_op op)
263{
264 printf("Error %s the chip: %d\n",
265 op == I2C_ERR_READ ? "reading" : "writing", ret);
266
267 return CMD_RET_FAILURE;
268}
269
270
271
272
273
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276
277
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279
280
281
282
283static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
284{
285 uint chip;
286 uint devaddr, length;
287 int alen;
288 u_char *memaddr;
289 int ret;
290#ifdef CONFIG_DM_I2C
291 struct udevice *dev;
292#endif
293
294 if (argc != 5)
295 return CMD_RET_USAGE;
296
297
298
299
300 chip = simple_strtoul(argv[1], NULL, 16);
301
302
303
304
305
306 devaddr = simple_strtoul(argv[2], NULL, 16);
307 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
308 if (alen > 3)
309 return CMD_RET_USAGE;
310
311
312
313
314 length = simple_strtoul(argv[3], NULL, 16);
315
316
317
318
319 memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
320
321#ifdef CONFIG_DM_I2C
322 ret = i2c_get_cur_bus_chip(chip, &dev);
323 if (!ret && alen != -1)
324 ret = i2c_set_chip_offset_len(dev, alen);
325 if (!ret)
326 ret = dm_i2c_read(dev, devaddr, memaddr, length);
327#else
328 ret = i2c_read(chip, devaddr, alen, memaddr, length);
329#endif
330 if (ret)
331 return i2c_report_err(ret, I2C_ERR_READ);
332
333 return 0;
334}
335
336static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
337{
338 uint chip;
339 uint devaddr, length;
340 int alen;
341 u_char *memaddr;
342 int ret;
343#ifdef CONFIG_DM_I2C
344 struct udevice *dev;
345 struct dm_i2c_chip *i2c_chip;
346#endif
347
348 if ((argc < 5) || (argc > 6))
349 return cmd_usage(cmdtp);
350
351
352
353
354 memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16);
355
356
357
358
359 chip = simple_strtoul(argv[2], NULL, 16);
360
361
362
363
364
365 devaddr = simple_strtoul(argv[3], NULL, 16);
366 alen = get_alen(argv[3], DEFAULT_ADDR_LEN);
367 if (alen > 3)
368 return cmd_usage(cmdtp);
369
370
371
372
373 length = simple_strtoul(argv[4], NULL, 16);
374
375#ifdef CONFIG_DM_I2C
376 ret = i2c_get_cur_bus_chip(chip, &dev);
377 if (!ret && alen != -1)
378 ret = i2c_set_chip_offset_len(dev, alen);
379 if (ret)
380 return i2c_report_err(ret, I2C_ERR_WRITE);
381 i2c_chip = dev_get_parent_platdata(dev);
382 if (!i2c_chip)
383 return i2c_report_err(ret, I2C_ERR_WRITE);
384#endif
385
386 if (argc == 6 && !strcmp(argv[5], "-s")) {
387
388
389
390
391
392
393#ifdef CONFIG_DM_I2C
394 i2c_chip->flags &= ~DM_I2C_CHIP_WR_ADDRESS;
395 ret = dm_i2c_write(dev, devaddr, memaddr, length);
396#else
397 ret = i2c_write(chip, devaddr, alen, memaddr, length);
398#endif
399 if (ret)
400 return i2c_report_err(ret, I2C_ERR_WRITE);
401 } else {
402
403
404
405
406 while (length-- > 0) {
407#ifdef CONFIG_DM_I2C
408 i2c_chip->flags |= DM_I2C_CHIP_WR_ADDRESS;
409 ret = dm_i2c_write(dev, devaddr++, memaddr++, 1);
410#else
411 ret = i2c_write(chip, devaddr++, alen, memaddr++, 1);
412#endif
413 if (ret)
414 return i2c_report_err(ret, I2C_ERR_WRITE);
415
416
417
418#if !defined(CONFIG_SYS_I2C_FRAM)
419 udelay(11000);
420#endif
421 }
422 }
423 return 0;
424}
425
426#ifdef CONFIG_DM_I2C
427static int do_i2c_flags(cmd_tbl_t *cmdtp, int flag, int argc,
428 char *const argv[])
429{
430 struct udevice *dev;
431 uint flags;
432 int chip;
433 int ret;
434
435 if (argc < 2)
436 return CMD_RET_USAGE;
437
438 chip = simple_strtoul(argv[1], NULL, 16);
439 ret = i2c_get_cur_bus_chip(chip, &dev);
440 if (ret)
441 return i2c_report_err(ret, I2C_ERR_READ);
442
443 if (argc > 2) {
444 flags = simple_strtoul(argv[2], NULL, 16);
445 ret = i2c_set_chip_flags(dev, flags);
446 } else {
447 ret = i2c_get_chip_flags(dev, &flags);
448 if (!ret)
449 printf("%x\n", flags);
450 }
451 if (ret)
452 return i2c_report_err(ret, I2C_ERR_READ);
453
454 return 0;
455}
456#endif
457
458
459
460
461
462
463
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465
466
467
468
469
470
471static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
472{
473 uint chip;
474 uint addr, length;
475 int alen;
476 int j, nbytes, linebytes;
477 int ret;
478#ifdef CONFIG_DM_I2C
479 struct udevice *dev;
480#endif
481
482
483
484
485 chip = i2c_dp_last_chip;
486 addr = i2c_dp_last_addr;
487 alen = i2c_dp_last_alen;
488 length = i2c_dp_last_length;
489
490 if (argc < 3)
491 return CMD_RET_USAGE;
492
493 if ((flag & CMD_FLAG_REPEAT) == 0) {
494
495
496
497
498
499
500
501 chip = simple_strtoul(argv[1], NULL, 16);
502
503
504
505
506
507 addr = simple_strtoul(argv[2], NULL, 16);
508 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
509 if (alen > 3)
510 return CMD_RET_USAGE;
511
512
513
514
515
516 if (argc > 3)
517 length = simple_strtoul(argv[3], NULL, 16);
518 }
519
520#ifdef CONFIG_DM_I2C
521 ret = i2c_get_cur_bus_chip(chip, &dev);
522 if (!ret && alen != -1)
523 ret = i2c_set_chip_offset_len(dev, alen);
524 if (ret)
525 return i2c_report_err(ret, I2C_ERR_READ);
526#endif
527
528
529
530
531
532
533
534 nbytes = length;
535 do {
536 unsigned char linebuf[DISP_LINE_LEN];
537 unsigned char *cp;
538
539 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
540
541#ifdef CONFIG_DM_I2C
542 ret = dm_i2c_read(dev, addr, linebuf, linebytes);
543#else
544 ret = i2c_read(chip, addr, alen, linebuf, linebytes);
545#endif
546 if (ret)
547 return i2c_report_err(ret, I2C_ERR_READ);
548 else {
549 printf("%04x:", addr);
550 cp = linebuf;
551 for (j=0; j<linebytes; j++) {
552 printf(" %02x", *cp++);
553 addr++;
554 }
555 puts (" ");
556 cp = linebuf;
557 for (j=0; j<linebytes; j++) {
558 if ((*cp < 0x20) || (*cp > 0x7e))
559 puts (".");
560 else
561 printf("%c", *cp);
562 cp++;
563 }
564 putc ('\n');
565 }
566 nbytes -= linebytes;
567 } while (nbytes > 0);
568
569 i2c_dp_last_chip = chip;
570 i2c_dp_last_addr = addr;
571 i2c_dp_last_alen = alen;
572 i2c_dp_last_length = length;
573
574 return 0;
575}
576
577
578
579
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581
582
583
584
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586
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588
589
590static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
591{
592 uint chip;
593 ulong addr;
594 int alen;
595 uchar byte;
596 int count;
597 int ret;
598#ifdef CONFIG_DM_I2C
599 struct udevice *dev;
600#endif
601
602 if ((argc < 4) || (argc > 5))
603 return CMD_RET_USAGE;
604
605
606
607
608 chip = simple_strtoul(argv[1], NULL, 16);
609
610
611
612
613 addr = simple_strtoul(argv[2], NULL, 16);
614 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
615 if (alen > 3)
616 return CMD_RET_USAGE;
617
618#ifdef CONFIG_DM_I2C
619 ret = i2c_get_cur_bus_chip(chip, &dev);
620 if (!ret && alen != -1)
621 ret = i2c_set_chip_offset_len(dev, alen);
622 if (ret)
623 return i2c_report_err(ret, I2C_ERR_WRITE);
624#endif
625
626
627
628 byte = simple_strtoul(argv[3], NULL, 16);
629
630
631
632
633 if (argc == 5)
634 count = simple_strtoul(argv[4], NULL, 16);
635 else
636 count = 1;
637
638 while (count-- > 0) {
639#ifdef CONFIG_DM_I2C
640 ret = dm_i2c_write(dev, addr++, &byte, 1);
641#else
642 ret = i2c_write(chip, addr++, alen, &byte, 1);
643#endif
644 if (ret)
645 return i2c_report_err(ret, I2C_ERR_WRITE);
646
647
648
649
650
651
652
653#if !defined(CONFIG_SYS_I2C_FRAM)
654 udelay(11000);
655#endif
656 }
657
658 return 0;
659}
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
677{
678 uint chip;
679 ulong addr;
680 int alen;
681 int count;
682 uchar byte;
683 ulong crc;
684 ulong err;
685 int ret = 0;
686#ifdef CONFIG_DM_I2C
687 struct udevice *dev;
688#endif
689
690 if (argc < 4)
691 return CMD_RET_USAGE;
692
693
694
695
696 chip = simple_strtoul(argv[1], NULL, 16);
697
698
699
700
701 addr = simple_strtoul(argv[2], NULL, 16);
702 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
703 if (alen > 3)
704 return CMD_RET_USAGE;
705
706#ifdef CONFIG_DM_I2C
707 ret = i2c_get_cur_bus_chip(chip, &dev);
708 if (!ret && alen != -1)
709 ret = i2c_set_chip_offset_len(dev, alen);
710 if (ret)
711 return i2c_report_err(ret, I2C_ERR_READ);
712#endif
713
714
715
716 count = simple_strtoul(argv[3], NULL, 16);
717
718 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
719
720
721
722
723 crc = 0;
724 err = 0;
725 while (count-- > 0) {
726#ifdef CONFIG_DM_I2C
727 ret = dm_i2c_read(dev, addr, &byte, 1);
728#else
729 ret = i2c_read(chip, addr, alen, &byte, 1);
730#endif
731 if (ret)
732 err++;
733 crc = crc32 (crc, &byte, 1);
734 addr++;
735 }
736 if (err > 0)
737 i2c_report_err(ret, I2C_ERR_READ);
738 else
739 printf ("%08lx\n", crc);
740
741 return 0;
742}
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760static int
761mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
762{
763 uint chip;
764 ulong addr;
765 int alen;
766 ulong data;
767 int size = 1;
768 int nbytes;
769 int ret;
770#ifdef CONFIG_DM_I2C
771 struct udevice *dev;
772#endif
773
774 if (argc != 3)
775 return CMD_RET_USAGE;
776
777 bootretry_reset_cmd_timeout();
778
779
780
781
782 chip = i2c_mm_last_chip;
783 addr = i2c_mm_last_addr;
784 alen = i2c_mm_last_alen;
785
786 if ((flag & CMD_FLAG_REPEAT) == 0) {
787
788
789
790
791 size = cmd_get_data_size(argv[0], 1);
792
793
794
795
796 chip = simple_strtoul(argv[1], NULL, 16);
797
798
799
800
801 addr = simple_strtoul(argv[2], NULL, 16);
802 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
803 if (alen > 3)
804 return CMD_RET_USAGE;
805 }
806
807#ifdef CONFIG_DM_I2C
808 ret = i2c_get_cur_bus_chip(chip, &dev);
809 if (!ret && alen != -1)
810 ret = i2c_set_chip_offset_len(dev, alen);
811 if (ret)
812 return i2c_report_err(ret, I2C_ERR_WRITE);
813#endif
814
815
816
817
818
819 do {
820 printf("%08lx:", addr);
821#ifdef CONFIG_DM_I2C
822 ret = dm_i2c_read(dev, addr, (uchar *)&data, size);
823#else
824 ret = i2c_read(chip, addr, alen, (uchar *)&data, size);
825#endif
826 if (ret)
827 return i2c_report_err(ret, I2C_ERR_READ);
828
829 data = cpu_to_be32(data);
830 if (size == 1)
831 printf(" %02lx", (data >> 24) & 0x000000FF);
832 else if (size == 2)
833 printf(" %04lx", (data >> 16) & 0x0000FFFF);
834 else
835 printf(" %08lx", data);
836
837 nbytes = cli_readline(" ? ");
838 if (nbytes == 0) {
839
840
841
842
843 if (incrflag)
844 addr += size;
845 nbytes = size;
846
847 bootretry_reset_cmd_timeout();
848 }
849#ifdef CONFIG_BOOT_RETRY_TIME
850 else if (nbytes == -2)
851 break;
852#endif
853 else {
854 char *endp;
855
856 data = simple_strtoul(console_buffer, &endp, 16);
857 if (size == 1)
858 data = data << 24;
859 else if (size == 2)
860 data = data << 16;
861 data = be32_to_cpu(data);
862 nbytes = endp - console_buffer;
863 if (nbytes) {
864
865
866
867 bootretry_reset_cmd_timeout();
868#ifdef CONFIG_DM_I2C
869 ret = dm_i2c_write(dev, addr, (uchar *)&data,
870 size);
871#else
872 ret = i2c_write(chip, addr, alen,
873 (uchar *)&data, size);
874#endif
875 if (ret)
876 return i2c_report_err(ret,
877 I2C_ERR_WRITE);
878#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
879 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
880#endif
881 if (incrflag)
882 addr += size;
883 }
884 }
885 } while (nbytes);
886
887 i2c_mm_last_chip = chip;
888 i2c_mm_last_addr = addr;
889 i2c_mm_last_alen = alen;
890
891 return 0;
892}
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
910{
911 int j;
912 int addr = -1;
913 int found = 0;
914#if defined(CONFIG_SYS_I2C_NOPROBES)
915 int k, skip;
916 unsigned int bus = GET_BUS_NUM;
917#endif
918 int ret;
919#ifdef CONFIG_DM_I2C
920 struct udevice *bus, *dev;
921
922 if (i2c_get_cur_bus(&bus))
923 return CMD_RET_FAILURE;
924#endif
925
926 if (argc == 2)
927 addr = simple_strtol(argv[1], 0, 16);
928
929 puts ("Valid chip addresses:");
930 for (j = 0; j < 128; j++) {
931 if ((0 <= addr) && (j != addr))
932 continue;
933
934#if defined(CONFIG_SYS_I2C_NOPROBES)
935 skip = 0;
936 for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
937 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
938 skip = 1;
939 break;
940 }
941 }
942 if (skip)
943 continue;
944#endif
945#ifdef CONFIG_DM_I2C
946 ret = dm_i2c_probe(bus, j, 0, &dev);
947#else
948 ret = i2c_probe(j);
949#endif
950 if (ret == 0) {
951 printf(" %02X", j);
952 found++;
953 }
954 }
955 putc ('\n');
956
957#if defined(CONFIG_SYS_I2C_NOPROBES)
958 puts ("Excluded chip addresses:");
959 for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
960 if (COMPARE_BUS(bus,k))
961 printf(" %02X", NO_PROBE_ADDR(k));
962 }
963 putc ('\n');
964#endif
965
966 return (0 == found);
967}
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
985{
986 uint chip;
987 int alen;
988 uint addr;
989 uint length;
990 u_char bytes[16];
991 int delay;
992 int ret;
993#ifdef CONFIG_DM_I2C
994 struct udevice *dev;
995#endif
996
997 if (argc < 3)
998 return CMD_RET_USAGE;
999
1000
1001
1002
1003 chip = simple_strtoul(argv[1], NULL, 16);
1004
1005
1006
1007
1008 addr = simple_strtoul(argv[2], NULL, 16);
1009 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
1010 if (alen > 3)
1011 return CMD_RET_USAGE;
1012#ifdef CONFIG_DM_I2C
1013 ret = i2c_get_cur_bus_chip(chip, &dev);
1014 if (!ret && alen != -1)
1015 ret = i2c_set_chip_offset_len(dev, alen);
1016 if (ret)
1017 return i2c_report_err(ret, I2C_ERR_WRITE);
1018#endif
1019
1020
1021
1022
1023 length = 1;
1024 length = simple_strtoul(argv[3], NULL, 16);
1025 if (length > sizeof(bytes))
1026 length = sizeof(bytes);
1027
1028
1029
1030
1031 delay = 1000;
1032 if (argc > 3)
1033 delay = simple_strtoul(argv[4], NULL, 10);
1034
1035
1036
1037 while (1) {
1038#ifdef CONFIG_DM_I2C
1039 ret = dm_i2c_read(dev, addr, bytes, length);
1040#else
1041 ret = i2c_read(chip, addr, alen, bytes, length);
1042#endif
1043 if (ret)
1044 i2c_report_err(ret, I2C_ERR_READ);
1045 udelay(delay);
1046 }
1047
1048
1049 return 0;
1050}
1051
1052
1053
1054
1055
1056
1057
1058#if defined(CONFIG_CMD_SDRAM)
1059static void print_ddr2_tcyc (u_char const b)
1060{
1061 printf ("%d.", (b >> 4) & 0x0F);
1062 switch (b & 0x0F) {
1063 case 0x0:
1064 case 0x1:
1065 case 0x2:
1066 case 0x3:
1067 case 0x4:
1068 case 0x5:
1069 case 0x6:
1070 case 0x7:
1071 case 0x8:
1072 case 0x9:
1073 printf ("%d ns\n", b & 0x0F);
1074 break;
1075 case 0xA:
1076 puts ("25 ns\n");
1077 break;
1078 case 0xB:
1079 puts ("33 ns\n");
1080 break;
1081 case 0xC:
1082 puts ("66 ns\n");
1083 break;
1084 case 0xD:
1085 puts ("75 ns\n");
1086 break;
1087 default:
1088 puts ("?? ns\n");
1089 break;
1090 }
1091}
1092
1093static void decode_bits (u_char const b, char const *str[], int const do_once)
1094{
1095 u_char mask;
1096
1097 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
1098 if (b & mask) {
1099 puts (*str);
1100 if (do_once)
1101 return;
1102 }
1103 }
1104}
1105
1106
1107
1108
1109
1110static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1111{
1112 enum { unknown, EDO, SDRAM, DDR2 } type;
1113
1114 uint chip;
1115 u_char data[128];
1116 u_char cksum;
1117 int j;
1118
1119 static const char *decode_CAS_DDR2[] = {
1120 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
1121 };
1122
1123 static const char *decode_CAS_default[] = {
1124 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
1125 };
1126
1127 static const char *decode_CS_WE_default[] = {
1128 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
1129 };
1130
1131 static const char *decode_byte21_default[] = {
1132 " TBD (bit 7)\n",
1133 " Redundant row address\n",
1134 " Differential clock input\n",
1135 " Registerd DQMB inputs\n",
1136 " Buffered DQMB inputs\n",
1137 " On-card PLL\n",
1138 " Registered address/control lines\n",
1139 " Buffered address/control lines\n"
1140 };
1141
1142 static const char *decode_byte22_DDR2[] = {
1143 " TBD (bit 7)\n",
1144 " TBD (bit 6)\n",
1145 " TBD (bit 5)\n",
1146 " TBD (bit 4)\n",
1147 " TBD (bit 3)\n",
1148 " Supports partial array self refresh\n",
1149 " Supports 50 ohm ODT\n",
1150 " Supports weak driver\n"
1151 };
1152
1153 static const char *decode_row_density_DDR2[] = {
1154 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
1155 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
1156 };
1157
1158 static const char *decode_row_density_default[] = {
1159 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
1160 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
1161 };
1162
1163 if (argc < 2)
1164 return CMD_RET_USAGE;
1165
1166
1167
1168
1169 chip = simple_strtoul (argv[1], NULL, 16);
1170
1171 if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
1172 puts ("No SDRAM Serial Presence Detect found.\n");
1173 return 1;
1174 }
1175
1176 cksum = 0;
1177 for (j = 0; j < 63; j++) {
1178 cksum += data[j];
1179 }
1180 if (cksum != data[63]) {
1181 printf ("WARNING: Configuration data checksum failure:\n"
1182 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
1183 }
1184 printf ("SPD data revision %d.%d\n",
1185 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
1186 printf ("Bytes used 0x%02X\n", data[0]);
1187 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
1188
1189 puts ("Memory type ");
1190 switch (data[2]) {
1191 case 2:
1192 type = EDO;
1193 puts ("EDO\n");
1194 break;
1195 case 4:
1196 type = SDRAM;
1197 puts ("SDRAM\n");
1198 break;
1199 case 8:
1200 type = DDR2;
1201 puts ("DDR2\n");
1202 break;
1203 default:
1204 type = unknown;
1205 puts ("unknown\n");
1206 break;
1207 }
1208
1209 puts ("Row address bits ");
1210 if ((data[3] & 0x00F0) == 0)
1211 printf ("%d\n", data[3] & 0x0F);
1212 else
1213 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
1214
1215 puts ("Column address bits ");
1216 if ((data[4] & 0x00F0) == 0)
1217 printf ("%d\n", data[4] & 0x0F);
1218 else
1219 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
1220
1221 switch (type) {
1222 case DDR2:
1223 printf ("Number of ranks %d\n",
1224 (data[5] & 0x07) + 1);
1225 break;
1226 default:
1227 printf ("Module rows %d\n", data[5]);
1228 break;
1229 }
1230
1231 switch (type) {
1232 case DDR2:
1233 printf ("Module data width %d bits\n", data[6]);
1234 break;
1235 default:
1236 printf ("Module data width %d bits\n",
1237 (data[7] << 8) | data[6]);
1238 break;
1239 }
1240
1241 puts ("Interface signal levels ");
1242 switch(data[8]) {
1243 case 0: puts ("TTL 5.0 V\n"); break;
1244 case 1: puts ("LVTTL\n"); break;
1245 case 2: puts ("HSTL 1.5 V\n"); break;
1246 case 3: puts ("SSTL 3.3 V\n"); break;
1247 case 4: puts ("SSTL 2.5 V\n"); break;
1248 case 5: puts ("SSTL 1.8 V\n"); break;
1249 default: puts ("unknown\n"); break;
1250 }
1251
1252 switch (type) {
1253 case DDR2:
1254 printf ("SDRAM cycle time ");
1255 print_ddr2_tcyc (data[9]);
1256 break;
1257 default:
1258 printf ("SDRAM cycle time %d.%d ns\n",
1259 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
1260 break;
1261 }
1262
1263 switch (type) {
1264 case DDR2:
1265 printf ("SDRAM access time 0.%d%d ns\n",
1266 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
1267 break;
1268 default:
1269 printf ("SDRAM access time %d.%d ns\n",
1270 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
1271 break;
1272 }
1273
1274 puts ("EDC configuration ");
1275 switch (data[11]) {
1276 case 0: puts ("None\n"); break;
1277 case 1: puts ("Parity\n"); break;
1278 case 2: puts ("ECC\n"); break;
1279 default: puts ("unknown\n"); break;
1280 }
1281
1282 if ((data[12] & 0x80) == 0)
1283 puts ("No self refresh, rate ");
1284 else
1285 puts ("Self refresh, rate ");
1286
1287 switch(data[12] & 0x7F) {
1288 case 0: puts ("15.625 us\n"); break;
1289 case 1: puts ("3.9 us\n"); break;
1290 case 2: puts ("7.8 us\n"); break;
1291 case 3: puts ("31.3 us\n"); break;
1292 case 4: puts ("62.5 us\n"); break;
1293 case 5: puts ("125 us\n"); break;
1294 default: puts ("unknown\n"); break;
1295 }
1296
1297 switch (type) {
1298 case DDR2:
1299 printf ("SDRAM width (primary) %d\n", data[13]);
1300 break;
1301 default:
1302 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
1303 if ((data[13] & 0x80) != 0) {
1304 printf (" (second bank) %d\n",
1305 2 * (data[13] & 0x7F));
1306 }
1307 break;
1308 }
1309
1310 switch (type) {
1311 case DDR2:
1312 if (data[14] != 0)
1313 printf ("EDC width %d\n", data[14]);
1314 break;
1315 default:
1316 if (data[14] != 0) {
1317 printf ("EDC width %d\n",
1318 data[14] & 0x7F);
1319
1320 if ((data[14] & 0x80) != 0) {
1321 printf (" (second bank) %d\n",
1322 2 * (data[14] & 0x7F));
1323 }
1324 }
1325 break;
1326 }
1327
1328 if (DDR2 != type) {
1329 printf ("Min clock delay, back-to-back random column addresses "
1330 "%d\n", data[15]);
1331 }
1332
1333 puts ("Burst length(s) ");
1334 if (data[16] & 0x80) puts (" Page");
1335 if (data[16] & 0x08) puts (" 8");
1336 if (data[16] & 0x04) puts (" 4");
1337 if (data[16] & 0x02) puts (" 2");
1338 if (data[16] & 0x01) puts (" 1");
1339 putc ('\n');
1340 printf ("Number of banks %d\n", data[17]);
1341
1342 switch (type) {
1343 case DDR2:
1344 puts ("CAS latency(s) ");
1345 decode_bits (data[18], decode_CAS_DDR2, 0);
1346 putc ('\n');
1347 break;
1348 default:
1349 puts ("CAS latency(s) ");
1350 decode_bits (data[18], decode_CAS_default, 0);
1351 putc ('\n');
1352 break;
1353 }
1354
1355 if (DDR2 != type) {
1356 puts ("CS latency(s) ");
1357 decode_bits (data[19], decode_CS_WE_default, 0);
1358 putc ('\n');
1359 }
1360
1361 if (DDR2 != type) {
1362 puts ("WE latency(s) ");
1363 decode_bits (data[20], decode_CS_WE_default, 0);
1364 putc ('\n');
1365 }
1366
1367 switch (type) {
1368 case DDR2:
1369 puts ("Module attributes:\n");
1370 if (data[21] & 0x80)
1371 puts (" TBD (bit 7)\n");
1372 if (data[21] & 0x40)
1373 puts (" Analysis probe installed\n");
1374 if (data[21] & 0x20)
1375 puts (" TBD (bit 5)\n");
1376 if (data[21] & 0x10)
1377 puts (" FET switch external enable\n");
1378 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
1379 if (data[20] & 0x11) {
1380 printf (" %d active registers on DIMM\n",
1381 (data[21] & 0x03) + 1);
1382 }
1383 break;
1384 default:
1385 puts ("Module attributes:\n");
1386 if (!data[21])
1387 puts (" (none)\n");
1388 else
1389 decode_bits (data[21], decode_byte21_default, 0);
1390 break;
1391 }
1392
1393 switch (type) {
1394 case DDR2:
1395 decode_bits (data[22], decode_byte22_DDR2, 0);
1396 break;
1397 default:
1398 puts ("Device attributes:\n");
1399 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1400 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1401 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1402 else puts (" Upper Vcc tolerance 10%\n");
1403 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1404 else puts (" Lower Vcc tolerance 10%\n");
1405 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1406 if (data[22] & 0x04) puts (" Supports precharge all\n");
1407 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1408 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1409 break;
1410 }
1411
1412 switch (type) {
1413 case DDR2:
1414 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1415 print_ddr2_tcyc (data[23]);
1416 break;
1417 default:
1418 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1419 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
1420 break;
1421 }
1422
1423 switch (type) {
1424 case DDR2:
1425 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1426 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1427 break;
1428 default:
1429 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1430 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1431 break;
1432 }
1433
1434 switch (type) {
1435 case DDR2:
1436 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1437 print_ddr2_tcyc (data[25]);
1438 break;
1439 default:
1440 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1441 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
1442 break;
1443 }
1444
1445 switch (type) {
1446 case DDR2:
1447 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1448 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1449 break;
1450 default:
1451 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1452 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1453 break;
1454 }
1455
1456 switch (type) {
1457 case DDR2:
1458 printf ("Minimum row precharge %d.%02d ns\n",
1459 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
1460 break;
1461 default:
1462 printf ("Minimum row precharge %d ns\n", data[27]);
1463 break;
1464 }
1465
1466 switch (type) {
1467 case DDR2:
1468 printf ("Row active to row active min %d.%02d ns\n",
1469 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
1470 break;
1471 default:
1472 printf ("Row active to row active min %d ns\n", data[28]);
1473 break;
1474 }
1475
1476 switch (type) {
1477 case DDR2:
1478 printf ("RAS to CAS delay min %d.%02d ns\n",
1479 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
1480 break;
1481 default:
1482 printf ("RAS to CAS delay min %d ns\n", data[29]);
1483 break;
1484 }
1485
1486 printf ("Minimum RAS pulse width %d ns\n", data[30]);
1487
1488 switch (type) {
1489 case DDR2:
1490 puts ("Density of each row ");
1491 decode_bits (data[31], decode_row_density_DDR2, 1);
1492 putc ('\n');
1493 break;
1494 default:
1495 puts ("Density of each row ");
1496 decode_bits (data[31], decode_row_density_default, 1);
1497 putc ('\n');
1498 break;
1499 }
1500
1501 switch (type) {
1502 case DDR2:
1503 puts ("Command and Address setup ");
1504 if (data[32] >= 0xA0) {
1505 printf ("1.%d%d ns\n",
1506 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
1507 } else {
1508 printf ("0.%d%d ns\n",
1509 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
1510 }
1511 break;
1512 default:
1513 printf ("Command and Address setup %c%d.%d ns\n",
1514 (data[32] & 0x80) ? '-' : '+',
1515 (data[32] >> 4) & 0x07, data[32] & 0x0F);
1516 break;
1517 }
1518
1519 switch (type) {
1520 case DDR2:
1521 puts ("Command and Address hold ");
1522 if (data[33] >= 0xA0) {
1523 printf ("1.%d%d ns\n",
1524 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
1525 } else {
1526 printf ("0.%d%d ns\n",
1527 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
1528 }
1529 break;
1530 default:
1531 printf ("Command and Address hold %c%d.%d ns\n",
1532 (data[33] & 0x80) ? '-' : '+',
1533 (data[33] >> 4) & 0x07, data[33] & 0x0F);
1534 break;
1535 }
1536
1537 switch (type) {
1538 case DDR2:
1539 printf ("Data signal input setup 0.%d%d ns\n",
1540 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
1541 break;
1542 default:
1543 printf ("Data signal input setup %c%d.%d ns\n",
1544 (data[34] & 0x80) ? '-' : '+',
1545 (data[34] >> 4) & 0x07, data[34] & 0x0F);
1546 break;
1547 }
1548
1549 switch (type) {
1550 case DDR2:
1551 printf ("Data signal input hold 0.%d%d ns\n",
1552 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
1553 break;
1554 default:
1555 printf ("Data signal input hold %c%d.%d ns\n",
1556 (data[35] & 0x80) ? '-' : '+',
1557 (data[35] >> 4) & 0x07, data[35] & 0x0F);
1558 break;
1559 }
1560
1561 puts ("Manufacturer's JEDEC ID ");
1562 for (j = 64; j <= 71; j++)
1563 printf ("%02X ", data[j]);
1564 putc ('\n');
1565 printf ("Manufacturing Location %02X\n", data[72]);
1566 puts ("Manufacturer's Part Number ");
1567 for (j = 73; j <= 90; j++)
1568 printf ("%02X ", data[j]);
1569 putc ('\n');
1570 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1571 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
1572 puts ("Assembly Serial Number ");
1573 for (j = 95; j <= 98; j++)
1574 printf ("%02X ", data[j]);
1575 putc ('\n');
1576
1577 if (DDR2 != type) {
1578 printf ("Speed rating PC%d\n",
1579 data[126] == 0x66 ? 66 : data[126]);
1580 }
1581 return 0;
1582}
1583#endif
1584
1585
1586
1587
1588
1589#if defined(CONFIG_I2C_EDID)
1590int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1591{
1592 uint chip;
1593 struct edid1_info edid;
1594 int ret;
1595#ifdef CONFIG_DM_I2C
1596 struct udevice *dev;
1597#endif
1598
1599 if (argc < 2) {
1600 cmd_usage(cmdtp);
1601 return 1;
1602 }
1603
1604 chip = simple_strtoul(argv[1], NULL, 16);
1605#ifdef CONFIG_DM_I2C
1606 ret = i2c_get_cur_bus_chip(chip, &dev);
1607 if (!ret)
1608 ret = dm_i2c_read(dev, 0, (uchar *)&edid, sizeof(edid));
1609#else
1610 ret = i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid));
1611#endif
1612 if (ret)
1613 return i2c_report_err(ret, I2C_ERR_READ);
1614
1615 if (edid_check_info(&edid)) {
1616 puts("Content isn't valid EDID.\n");
1617 return 1;
1618 }
1619
1620 edid_print_info(&edid);
1621 return 0;
1622
1623}
1624#endif
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635#if defined(CONFIG_SYS_I2C)
1636static int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc,
1637 char * const argv[])
1638{
1639 int i;
1640#ifndef CONFIG_SYS_I2C_DIRECT_BUS
1641 int j;
1642#endif
1643
1644 if (argc == 1) {
1645
1646 for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) {
1647 printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1648#ifndef CONFIG_SYS_I2C_DIRECT_BUS
1649 for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1650 if (i2c_bus[i].next_hop[j].chip == 0)
1651 break;
1652 printf("->%s@0x%2x:%d",
1653 i2c_bus[i].next_hop[j].mux.name,
1654 i2c_bus[i].next_hop[j].chip,
1655 i2c_bus[i].next_hop[j].channel);
1656 }
1657#endif
1658 printf("\n");
1659 }
1660 } else {
1661
1662 i = simple_strtoul(argv[1], NULL, 10);
1663 if (i >= CONFIG_SYS_NUM_I2C_BUSES) {
1664 printf("Invalid bus %d\n", i);
1665 return -1;
1666 }
1667 printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1668#ifndef CONFIG_SYS_I2C_DIRECT_BUS
1669 for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1670 if (i2c_bus[i].next_hop[j].chip == 0)
1671 break;
1672 printf("->%s@0x%2x:%d",
1673 i2c_bus[i].next_hop[j].mux.name,
1674 i2c_bus[i].next_hop[j].chip,
1675 i2c_bus[i].next_hop[j].channel);
1676 }
1677#endif
1678 printf("\n");
1679 }
1680
1681 return 0;
1682}
1683#endif
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) || \
1696 defined(CONFIG_DM_I2C)
1697static int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc,
1698 char * const argv[])
1699{
1700 int ret = 0;
1701 int bus_no;
1702
1703 if (argc == 1) {
1704
1705#ifdef CONFIG_DM_I2C
1706 struct udevice *bus;
1707
1708 if (!i2c_get_cur_bus(&bus))
1709 bus_no = bus->seq;
1710 else
1711 bus_no = -1;
1712#else
1713 bus_no = i2c_get_bus_num();
1714#endif
1715 printf("Current bus is %d\n", bus_no);
1716 } else {
1717 bus_no = simple_strtoul(argv[1], NULL, 10);
1718#if defined(CONFIG_SYS_I2C)
1719 if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
1720 printf("Invalid bus %d\n", bus_no);
1721 return -1;
1722 }
1723#endif
1724 printf("Setting bus to %d\n", bus_no);
1725#ifdef CONFIG_DM_I2C
1726 ret = cmd_i2c_set_bus_num(bus_no);
1727#else
1728 ret = i2c_set_bus_num(bus_no);
1729#endif
1730 if (ret)
1731 printf("Failure changing bus number (%d)\n", ret);
1732 }
1733 return ret;
1734}
1735#endif
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1748{
1749 int speed, ret=0;
1750
1751#ifdef CONFIG_DM_I2C
1752 struct udevice *bus;
1753
1754 if (i2c_get_cur_bus(&bus))
1755 return 1;
1756#endif
1757 if (argc == 1) {
1758#ifdef CONFIG_DM_I2C
1759 speed = dm_i2c_get_bus_speed(bus);
1760#else
1761 speed = i2c_get_bus_speed();
1762#endif
1763
1764 printf("Current bus speed=%d\n", speed);
1765 } else {
1766 speed = simple_strtoul(argv[1], NULL, 10);
1767 printf("Setting bus speed to %d Hz\n", speed);
1768#ifdef CONFIG_DM_I2C
1769 ret = dm_i2c_set_bus_speed(bus, speed);
1770#else
1771 ret = i2c_set_bus_speed(speed);
1772#endif
1773 if (ret)
1774 printf("Failure changing bus speed (%d)\n", ret);
1775 }
1776 return ret;
1777}
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1790{
1791 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
1792}
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1805{
1806 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
1807}
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1819{
1820#if defined(CONFIG_DM_I2C)
1821 struct udevice *bus;
1822
1823 if (i2c_get_cur_bus(&bus))
1824 return CMD_RET_FAILURE;
1825 if (i2c_deblock(bus)) {
1826 printf("Error: Not supported by the driver\n");
1827 return CMD_RET_FAILURE;
1828 }
1829#elif defined(CONFIG_SYS_I2C)
1830 i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr);
1831#else
1832 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
1833#endif
1834 return 0;
1835}
1836
1837static cmd_tbl_t cmd_i2c_sub[] = {
1838#if defined(CONFIG_SYS_I2C)
1839 U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
1840#endif
1841 U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
1842#if defined(CONFIG_SYS_I2C) || \
1843 defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
1844 U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
1845#endif
1846#if defined(CONFIG_I2C_EDID)
1847 U_BOOT_CMD_MKENT(edid, 1, 1, do_edid, "", ""),
1848#endif
1849 U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
1850 U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
1851 U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
1852 U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
1853 U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
1854 U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
1855 U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
1856 U_BOOT_CMD_MKENT(write, 6, 0, do_i2c_write, "", ""),
1857#ifdef CONFIG_DM_I2C
1858 U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""),
1859#endif
1860 U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
1861#if defined(CONFIG_CMD_SDRAM)
1862 U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
1863#endif
1864 U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
1865};
1866
1867#ifdef CONFIG_NEEDS_MANUAL_RELOC
1868void i2c_reloc(void) {
1869 fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
1870}
1871#endif
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1884{
1885 cmd_tbl_t *c;
1886
1887 if (argc < 2)
1888 return CMD_RET_USAGE;
1889
1890
1891 argc--;
1892 argv++;
1893
1894 c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
1895
1896 if (c)
1897 return c->cmd(cmdtp, flag, argc, argv);
1898 else
1899 return CMD_RET_USAGE;
1900}
1901
1902
1903#ifdef CONFIG_SYS_LONGHELP
1904static char i2c_help_text[] =
1905#if defined(CONFIG_SYS_I2C)
1906 "bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
1907#endif
1908 "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
1909#if defined(CONFIG_SYS_I2C) || \
1910 defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
1911 "i2c dev [dev] - show or set current I2C bus\n"
1912#endif
1913#if defined(CONFIG_I2C_EDID)
1914 "i2c edid chip - print EDID configuration information\n"
1915#endif
1916 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
1917 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
1918 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
1919 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
1920 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
1921 "i2c probe [address] - test for and show device(s) on the I2C bus\n"
1922 "i2c read chip address[.0, .1, .2] length memaddress - read to memory\n"
1923 "i2c write memaddress chip address[.0, .1, .2] length [-s] - write memory\n"
1924 " to I2C; the -s option selects bulk write in a single transaction\n"
1925#ifdef CONFIG_DM_I2C
1926 "i2c flags chip [flags] - set or get chip flags\n"
1927#endif
1928 "i2c reset - re-init the I2C Controller\n"
1929#if defined(CONFIG_CMD_SDRAM)
1930 "i2c sdram chip - print SDRAM configuration information\n"
1931#endif
1932 "i2c speed [speed] - show or set I2C bus speed";
1933#endif
1934
1935U_BOOT_CMD(
1936 i2c, 7, 1, do_i2c,
1937 "I2C sub-system",
1938 i2c_help_text
1939);
1940