LXR uboot/drivers/block/mvsata

   1/*
   2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
   3 *
   4 * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#include <common.h>
  10#include <asm/io.h>
  11
  12#if defined(CONFIG_ORION5X)
  13#include <asm/arch/orion5x.h>
  14#elif defined(CONFIG_KIRKWOOD)
  15#include <asm/arch/soc.h>
  16#endif
  17
  18/* SATA port registers */
  19struct mvsata_port_registers {
  20        u32 reserved0[10];
  21        u32 edma_cmd;
  22        u32 reserved1[181];
  23        /* offset 0x300 : ATA Interface registers */
  24        u32 sstatus;
  25        u32 serror;
  26        u32 scontrol;
  27        u32 ltmode;
  28        u32 phymode3;
  29        u32 phymode4;
  30        u32 reserved2[5];
  31        u32 phymode1;
  32        u32 phymode2;
  33        u32 bist_cr;
  34        u32 bist_dw1;
  35        u32 bist_dw2;
  36        u32 serrorintrmask;
  37};
  38
  39/*
  40 * Sanity checks:
  41 * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
  42 * - for ide_preinit to make sense, we need at least one of
  43 *   CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET;
  44 * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT.
  45 * Fail with an explanation message if these conditions are not met.
  46 * This is particularly important for CONFIG_IDE_PREINIT, because
  47 * its lack would not cause a build error.
  48 */
  49
  50#if !defined(CONFIG_SYS_ATA_BASE_ADDR)
  51#error CONFIG_SYS_ATA_BASE_ADDR must be defined
  52#elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \
  53   && !defined(CONFIG_SYS_ATA_IDE1_OFFSET)
  54#error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \
  55   must be defined
  56#elif !defined(CONFIG_IDE_PREINIT)
  57#error CONFIG_IDE_PREINIT must be defined
  58#endif
  59
  60/*
  61 * Masks and values for SControl DETection and Interface Power Management,
  62 * and for SStatus DETection.
  63 */
  64
  65#define MVSATA_EDMA_CMD_ATA_RST         0x00000004
  66#define MVSATA_SCONTROL_DET_MASK                0x0000000F
  67#define MVSATA_SCONTROL_DET_NONE                0x00000000
  68#define MVSATA_SCONTROL_DET_INIT                0x00000001
  69#define MVSATA_SCONTROL_IPM_MASK                0x00000F00
  70#define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED       0x00000300
  71#define MVSATA_SCONTROL_MASK \
  72        (MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK)
  73#define MVSATA_PORT_INIT \
  74        (MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
  75#define MVSATA_PORT_USE \
  76        (MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
  77#define MVSATA_SSTATUS_DET_MASK                 0x0000000F
  78#define MVSATA_SSTATUS_DET_DEVCOMM              0x00000003
  79
  80/*
  81 * Status codes to return to client callers. Currently, callers ignore
  82 * exact value and only care for zero or nonzero, so no need to make this
  83 * public, it is only #define'd for clarity.
  84 * If/when standard negative codes are implemented in U-boot, then these
  85 * #defines should be moved to, or replaced by ones from, the common list
  86 * of status codes.
  87 */
  88
  89#define MVSATA_STATUS_OK        0
  90#define MVSATA_STATUS_TIMEOUT   -1
  91
  92/*
  93 * Initialize one MVSATAHC port: set SControl's IPM to "always active"
  94 * and DET to "reset", then wait for SStatus's DET to become "device and
  95 * comm ok" (or time out after 50 us if no device), then set SControl's
  96 * DET back to "no action".
  97 */
  98
  99static int mvsata_ide_initialize_port(struct mvsata_port_registers *port)
 100{
 101        u32 control;
 102        u32 status;
 103        u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */
 104
 105        /* Hard reset */
 106        writel(MVSATA_EDMA_CMD_ATA_RST, &port->edma_cmd);
 107        udelay(25); /* taken from original marvell port */
 108        writel(0, &port->edma_cmd);
 109
 110        /* Set control IPM to 3 (no low power) and DET to 1 (initialize) */
 111        control = readl(&port->scontrol);
 112        control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;
 113        writel(control, &port->scontrol);
 114        /* Toggle control DET back to 0 (normal operation) */
 115        control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
 116        writel(control, &port->scontrol);
 117        /* wait for status DET to become 3 (device and communication OK) */
 118        while (--timeleft) {
 119                status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK;
 120                if (status == MVSATA_SSTATUS_DET_DEVCOMM)
 121                        break;
 122                udelay(1);
 123        }
 124        /* return success or time-out error depending on time left */
 125        if (!timeleft)
 126                return MVSATA_STATUS_TIMEOUT;
 127        return MVSATA_STATUS_OK;
 128}
 129
 130/*
 131 * ide_preinit() will be called by ide_init in cmd_ide.c and will
 132 * reset the MVSTATHC ports needed by the board.
 133 */
 134
 135int ide_preinit(void)
 136{
 137        int ret = MVSATA_STATUS_TIMEOUT;
 138        int status;
 139
 140        /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
 141#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
 142        status = mvsata_ide_initialize_port(
 143                (struct mvsata_port_registers *)
 144                (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET));
 145        if (status == MVSATA_STATUS_OK)
 146                ret = MVSATA_STATUS_OK;
 147#endif
 148        /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */
 149#if defined(CONFIG_SYS_ATA_IDE1_OFFSET)
 150        status = mvsata_ide_initialize_port(
 151                (struct mvsata_port_registers *)
 152                (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET));
 153        if (status == MVSATA_STATUS_OK)
 154                ret = MVSATA_STATUS_OK;
 155#endif
 156        /* Return success if at least one port initialization succeeded */
 157        return ret;
 158}
 159