LXR uboot/drivers/i2c/sh

   1/*
   2 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
   3 * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <i2c.h>
  10#include <asm/io.h>
  11
  12DECLARE_GLOBAL_DATA_PTR;
  13
  14/* Every register is 32bit aligned, but only 8bits in size */
  15#define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
  16struct sh_i2c {
  17        ureg(icdr);
  18        ureg(iccr);
  19        ureg(icsr);
  20        ureg(icic);
  21        ureg(iccl);
  22        ureg(icch);
  23};
  24#undef ureg
  25
  26/* ICCR */
  27#define SH_I2C_ICCR_ICE         (1 << 7)
  28#define SH_I2C_ICCR_RACK        (1 << 6)
  29#define SH_I2C_ICCR_RTS         (1 << 4)
  30#define SH_I2C_ICCR_BUSY        (1 << 2)
  31#define SH_I2C_ICCR_SCP         (1 << 0)
  32
  33/* ICSR / ICIC */
  34#define SH_IC_BUSY      (1 << 4)
  35#define SH_IC_TACK      (1 << 2)
  36#define SH_IC_WAIT      (1 << 1)
  37#define SH_IC_DTE       (1 << 0)
  38
  39#ifdef CONFIG_SH_I2C_8BIT
  40/* store 8th bit of iccl and icch in ICIC register */
  41#define SH_I2C_ICIC_ICCLB8      (1 << 7)
  42#define SH_I2C_ICIC_ICCHB8      (1 << 6)
  43#endif
  44
  45static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
  46        (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
  47#ifdef CONFIG_SYS_I2C_SH_BASE1
  48        (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
  49#endif
  50#ifdef CONFIG_SYS_I2C_SH_BASE2
  51        (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
  52#endif
  53#ifdef CONFIG_SYS_I2C_SH_BASE3
  54        (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
  55#endif
  56#ifdef CONFIG_SYS_I2C_SH_BASE4
  57        (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
  58#endif
  59};
  60
  61static u16 iccl, icch;
  62
  63#define IRQ_WAIT 1000
  64
  65static void sh_irq_dte(struct sh_i2c *dev)
  66{
  67        int i;
  68
  69        for (i = 0; i < IRQ_WAIT; i++) {
  70                if (SH_IC_DTE & readb(&dev->icsr))
  71                        break;
  72                udelay(10);
  73        }
  74}
  75
  76static int sh_irq_dte_with_tack(struct sh_i2c *dev)
  77{
  78        int i;
  79
  80        for (i = 0; i < IRQ_WAIT; i++) {
  81                if (SH_IC_DTE & readb(&dev->icsr))
  82                        break;
  83                if (SH_IC_TACK & readb(&dev->icsr))
  84                        return -1;
  85                udelay(10);
  86        }
  87        return 0;
  88}
  89
  90static void sh_irq_busy(struct sh_i2c *dev)
  91{
  92        int i;
  93
  94        for (i = 0; i < IRQ_WAIT; i++) {
  95                if (!(SH_IC_BUSY & readb(&dev->icsr)))
  96                        break;
  97                udelay(10);
  98        }
  99}
 100
 101static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
 102{
 103        u8 icic = SH_IC_TACK;
 104
 105        debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
 106                                __func__, chip, addr, iccl, icch);
 107        clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
 108        setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
 109
 110        writeb(iccl & 0xff, &dev->iccl);
 111        writeb(icch & 0xff, &dev->icch);
 112#ifdef CONFIG_SH_I2C_8BIT
 113        if (iccl > 0xff)
 114                icic |= SH_I2C_ICIC_ICCLB8;
 115        if (icch > 0xff)
 116                icic |= SH_I2C_ICIC_ICCHB8;
 117#endif
 118        writeb(icic, &dev->icic);
 119
 120        writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
 121        sh_irq_dte(dev);
 122
 123        clrbits_8(&dev->icsr, SH_IC_TACK);
 124        writeb(chip << 1, &dev->icdr);
 125        if (sh_irq_dte_with_tack(dev) != 0)
 126                return -1;
 127
 128        writeb(addr, &dev->icdr);
 129        if (stop)
 130                writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
 131
 132        if (sh_irq_dte_with_tack(dev) != 0)
 133                return -1;
 134        return 0;
 135}
 136
 137static void sh_i2c_finish(struct sh_i2c *dev)
 138{
 139        writeb(0, &dev->icsr);
 140        clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
 141}
 142
 143static int
 144sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
 145{
 146        int ret = -1;
 147        if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
 148                goto exit0;
 149        udelay(10);
 150
 151        writeb(val, &dev->icdr);
 152        if (sh_irq_dte_with_tack(dev) != 0)
 153                goto exit0;
 154
 155        writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
 156        if (sh_irq_dte_with_tack(dev) != 0)
 157                goto exit0;
 158        sh_irq_busy(dev);
 159        ret = 0;
 160
 161exit0:
 162        sh_i2c_finish(dev);
 163        return ret;
 164}
 165
 166static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
 167{
 168        int ret = -1;
 169
 170#if defined(CONFIG_SH73A0)
 171        if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
 172                goto exit0;
 173#else
 174        if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
 175                goto exit0;
 176        udelay(100);
 177#endif
 178
 179        writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
 180        sh_irq_dte(dev);
 181
 182        writeb(chip << 1 | 0x01, &dev->icdr);
 183        if (sh_irq_dte_with_tack(dev) != 0)
 184                goto exit0;
 185
 186        writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
 187        if (sh_irq_dte_with_tack(dev) != 0)
 188                goto exit0;
 189
 190        ret = readb(&dev->icdr) & 0xff;
 191
 192        writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
 193        readb(&dev->icdr); /* Dummy read */
 194        sh_irq_busy(dev);
 195
 196exit0:
 197        sh_i2c_finish(dev);
 198
 199        return ret;
 200}
 201
 202static void
 203sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 204{
 205        int num, denom, tmp;
 206
 207        /* No i2c support prior to relocation */
 208        if (!(gd->flags & GD_FLG_RELOC))
 209                return;
 210
 211        /*
 212         * Calculate the value for iccl. From the data sheet:
 213         * iccl = (p-clock / transfer-rate) * (L / (L + H))
 214         * where L and H are the SCL low and high ratio.
 215         */
 216        num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
 217        denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
 218        tmp = num * 10 / denom;
 219        if (tmp % 10 >= 5)
 220                iccl = (u16)((num/denom) + 1);
 221        else
 222                iccl = (u16)(num/denom);
 223
 224        /* Calculate the value for icch. From the data sheet:
 225           icch = (p clock / transfer rate) * (H / (L + H)) */
 226        num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
 227        tmp = num * 10 / denom;
 228        if (tmp % 10 >= 5)
 229                icch = (u16)((num/denom) + 1);
 230        else
 231                icch = (u16)(num/denom);
 232
 233        debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
 234                        CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
 235}
 236
 237static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
 238                                uint addr, int alen, u8 *data, int len)
 239{
 240        int ret, i;
 241        struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
 242
 243        for (i = 0; i < len; i++) {
 244                ret = sh_i2c_raw_read(dev, chip, addr + i);
 245                if (ret < 0)
 246                        return -1;
 247
 248                data[i] = ret & 0xff;
 249                debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
 250        }
 251
 252        return 0;
 253}
 254
 255static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
 256                                int alen, u8 *data, int len)
 257{
 258        struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
 259        int i;
 260
 261        for (i = 0; i < len; i++) {
 262                debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
 263                if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
 264                        return -1;
 265        }
 266        return 0;
 267}
 268
 269static int
 270sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
 271{
 272        u8 dummy[1];
 273
 274        return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
 275}
 276
 277static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
 278                        unsigned int speed)
 279{
 280        struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
 281
 282        sh_i2c_finish(dev);
 283        sh_i2c_init(adap, speed, 0);
 284
 285        return 0;
 286}
 287
 288/*
 289 * Register RCAR i2c adapters
 290 */
 291U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 292        sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
 293#ifdef CONFIG_SYS_I2C_SH_BASE1
 294U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 295        sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
 296#endif
 297#ifdef CONFIG_SYS_I2C_SH_BASE2
 298U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 299        sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
 300#endif
 301#ifdef CONFIG_SYS_I2C_SH_BASE3
 302U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 303        sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
 304#endif
 305#ifdef CONFIG_SYS_I2C_SH_BASE4
 306U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
 307        sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
 308#endif
 309