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14#include <common.h>
15#include <i2c.h>
16
17#include "u8500_i2c.h"
18#include <asm/io.h>
19#include <asm/arch/clock.h>
20
21#define U8500_I2C_ENDAD_COUNTER (CONFIG_SYS_HZ/100)
22#define U8500_I2C_FIFO_FLUSH_COUNTER 500000
23#define U8500_I2C_SCL_FREQ 100000
24#define U8500_I2C_INPUT_FREQ 48000000
25#define TX_FIFO_THRESHOLD 0x4
26#define RX_FIFO_THRESHOLD 0x4
27#define SLAVE_SETUP_TIME 14
28
29#define WRITE_FIELD(var, mask, shift, value) \
30 (var = ((var & ~(mask)) | ((value) << (shift))))
31
32static unsigned int bus_initialized[CONFIG_SYS_U8500_I2C_BUS_MAX];
33static unsigned int i2c_bus_num;
34static unsigned int i2c_bus_speed[] = {
35 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED,
36 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED
37};
38static struct u8500_i2c_regs *i2c_dev[] = {
39 (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C0_BASE,
40 (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C1_BASE,
41 (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C2_BASE,
42 (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C3_BASE,
43};
44
45static struct {
46 int periph;
47 int pcken;
48 int kcken;
49} i2c_clock_bits[] = {
50 {3, 3, 3},
51 {1, 2, 2},
52 {1, 6, 6},
53 {2, 0, 0},
54};
55
56static void i2c_set_bit(void *reg, u32 mask)
57{
58 writel(readl(reg) | mask, reg);
59}
60
61static void i2c_clr_bit(void *reg, u32 mask)
62{
63 writel(readl(reg) & ~mask, reg);
64}
65
66static void i2c_write_field(void *reg, u32 mask, uint shift, u32 value)
67{
68 writel((readl(reg) & ~mask) | (value << shift), reg);
69}
70
71static int __i2c_set_bus_speed(unsigned int speed)
72{
73 u32 value;
74 struct u8500_i2c_regs *i2c_regs;
75
76 i2c_regs = i2c_dev[i2c_bus_num];
77
78
79 i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_SM,
80 U8500_I2C_CR_SHIFT_SM, 0x0);
81
82
83
84
85
86
87 value = (u32) (U8500_I2C_INPUT_FREQ / (speed * 2));
88 i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT2,
89 U8500_I2C_BRCR_SHIFT_BRCNT2, value);
90
91
92 i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT1,
93 U8500_I2C_BRCR_SHIFT_BRCNT1, 0);
94
95 return U8500_I2C_INPUT_FREQ/(value * 2);
96}
97
98
99
100
101
102
103
104
105
106void i2c_init(int speed, int slaveaddr)
107{
108 struct u8500_i2c_regs *i2c_regs;
109
110 debug("i2c_init bus %d, speed %d\n", i2c_bus_num, speed);
111
112 u8500_clock_enable(i2c_clock_bits[i2c_bus_num].periph,
113 i2c_clock_bits[i2c_bus_num].pcken,
114 i2c_clock_bits[i2c_bus_num].kcken);
115
116 i2c_regs = i2c_dev[i2c_bus_num];
117
118
119 i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
120
121
122 writel(0, &i2c_regs->cr);
123 writel(0, &i2c_regs->scr);
124 writel(0, &i2c_regs->hsmcr);
125 writel(0, &i2c_regs->tftr);
126 writel(0, &i2c_regs->rftr);
127 writel(0, &i2c_regs->dmar);
128
129 i2c_bus_speed[i2c_bus_num] = __i2c_set_bus_speed(speed);
130
131
132
133
134
135 i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_SAM);
136 i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_ADDR,
137 U8500_I2C_SCR_SHIFT_ADDR, slaveaddr);
138
139 i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_DATA_SETUP_TIME,
140 U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME, SLAVE_SETUP_TIME);
141
142
143 i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_DMA_SLE,
144 U8500_I2C_CR_SHIFT_DMA_SLE, 0);
145
146
147 writel(0, &i2c_regs->imscr);
148
149
150 i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_OM, U8500_I2C_CR_SHIFT_OM,
151 U8500_I2C_BUS_MASTER_MODE);
152
153 writel(TX_FIFO_THRESHOLD, &i2c_regs->tftr);
154 writel(RX_FIFO_THRESHOLD, &i2c_regs->rftr);
155
156
157 i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
158
159 bus_initialized[i2c_bus_num] = 1;
160}
161
162
163
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165
166
167
168
169static int loop_till_bit_clear(void *io_reg, u32 mask, unsigned long timeout)
170{
171 unsigned long timebase = get_timer(0);
172
173 do {
174 if ((readl(io_reg) & mask) == 0x0UL)
175 return 0;
176 } while (get_timer(timebase) < timeout);
177
178 debug("loop_till_bit_clear timed out\n");
179 return -1;
180}
181
182
183
184
185
186
187
188static int loop_till_bit_set(void *io_reg, u32 mask, unsigned long timeout)
189{
190 unsigned long timebase = get_timer(0);
191
192 do {
193 if ((readl(io_reg) & mask) != 0x0UL)
194 return 0;
195 } while (get_timer(timebase) < timeout);
196
197 debug("loop_till_bit_set timed out\n");
198 return -1;
199}
200
201
202
203
204static void flush_fifo(struct u8500_i2c_regs *i2c_regs)
205{
206 int counter = U8500_I2C_FIFO_FLUSH_COUNTER;
207
208
209 i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FTX);
210
211 i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FRX);
212 while (counter--) {
213 if (!(readl(&i2c_regs->cr) &
214 (U8500_I2C_CR_FTX | U8500_I2C_CR_FRX)))
215 break;
216 }
217 return;
218}
219
220#ifdef DEBUG
221static void print_abort_reason(struct u8500_i2c_regs *i2c_regs)
222{
223 int cause;
224
225 printf("abort: risr %08x, sr %08x\n", i2c_regs->risr, i2c_regs->sr);
226 cause = (readl(&i2c_regs->sr) & U8500_I2C_SR_CAUSE) >>
227 U8500_I2C_SR_SHIFT_CAUSE;
228 switch (cause) {
229 case U8500_I2C_NACK_ADDR:
230 printf("No Ack received after Slave Address xmission\n");
231 break;
232 case U8500_I2C_NACK_DATA:
233 printf("Valid for MASTER_WRITE: No Ack received "
234 "during data phase\n");
235 break;
236 case U8500_I2C_ACK_MCODE:
237 printf("Master recv ack after xmission of master code"
238 "in hs mode\n");
239 break;
240 case U8500_I2C_ARB_LOST:
241 printf("Master Lost arbitration\n");
242 break;
243 case U8500_I2C_BERR_START:
244 printf("Slave restarts\n");
245 break;
246 case U8500_I2C_BERR_STOP:
247 printf("Slave reset\n");
248 break;
249 case U8500_I2C_OVFL:
250 printf("Overflow\n");
251 break;
252 default:
253 printf("Unknown error type\n");
254 }
255}
256#endif
257
258
259
260
261static void i2c_abort(struct u8500_i2c_regs *i2c_regs)
262{
263#ifdef DEBUG
264 print_abort_reason(i2c_regs);
265#endif
266
267 flush_fifo(i2c_regs);
268
269
270 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
271
272
273 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
274
275 i2c_init(i2c_bus_speed[i2c_bus_num], CONFIG_SYS_I2C_SLAVE);
276}
277
278
279
280
281static int i2c_write_addr(struct u8500_i2c_regs *i2c_regs, uint addr, int alen)
282{
283 while (alen--) {
284
285 if (loop_till_bit_clear((void *)&i2c_regs->risr,
286 U8500_I2C_INT_TXFF,
287 U8500_I2C_ENDAD_COUNTER)) {
288 i2c_abort(i2c_regs);
289 return -1;
290 }
291
292
293 writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->tfr);
294 }
295
296 return 0;
297}
298
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308
309
310static int i2c_read_byte(struct u8500_i2c_regs *i2c_regs, uchar chip,
311 uint addr, int alen, uchar *value)
312{
313 u32 mcr = 0;
314
315
316 WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
317
318
319 WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
320
321 if (alen != 0) {
322
323 mcr &= ~(U8500_I2C_MCR_OP);
324
325
326 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH,
327 U8500_I2C_MCR_SHIFT_LENGTH, 1);
328
329
330 mcr &= ~(U8500_I2C_MCR_STOP);
331
332
333 writel(mcr, &i2c_regs->mcr);
334
335
336 if (i2c_write_addr(i2c_regs, addr, alen) != 0)
337 return -1;
338
339
340 if (loop_till_bit_set((void *)&i2c_regs->risr,
341 U8500_I2C_INT_MTDWS,
342 U8500_I2C_ENDAD_COUNTER)) {
343 return -1;
344 }
345
346
347 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
348 }
349
350
351 mcr |= U8500_I2C_MCR_OP;
352
353
354 mcr |= U8500_I2C_MCR_STOP;
355
356
357 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
358
359 i2c_write_field(&i2c_regs->mcr, U8500_I2C_MCR_LENGTH_STOP_OP,
360 U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP, mcr);
361
362
363
364
365
366
367 if (loop_till_bit_clear((void *)&i2c_regs->risr,
368 U8500_I2C_INT_RXFE,
369 U8500_I2C_ENDAD_COUNTER))
370 return -1;
371
372
373 *value = readb(&i2c_regs->rfr);
374
375
376 if (loop_till_bit_set((void *)&i2c_regs->risr, U8500_I2C_INT_MTD,
377 U8500_I2C_ENDAD_COUNTER))
378 return -1;
379
380
381 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
382
383
384 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
385
386 return 0;
387}
388
389
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397
398
399
400
401static int __i2c_write(struct u8500_i2c_regs *i2c_regs, u8 chip, uint addr,
402 int alen, u8 *data, int len)
403{
404 int i;
405 u32 mcr = 0;
406
407
408 WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
409
410
411 WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
412
413
414 mcr &= ~(U8500_I2C_MCR_OP);
415
416
417 mcr |= U8500_I2C_MCR_STOP;
418
419
420 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH,
421 (alen + len));
422
423
424 writel(mcr, &i2c_regs->mcr);
425
426 if (i2c_write_addr(i2c_regs, addr, alen) != 0)
427 return -1;
428
429 for (i = 0; i < len; i++) {
430
431 if (loop_till_bit_clear((void *)&i2c_regs->risr,
432 U8500_I2C_INT_TXFF,
433 U8500_I2C_ENDAD_COUNTER))
434 return -1;
435
436
437 writeb(data[i], &i2c_regs->tfr);
438 }
439
440
441 if (loop_till_bit_set((void *)&i2c_regs->risr,
442 U8500_I2C_INT_MTD,
443 U8500_I2C_ENDAD_COUNTER)) {
444 printf("i2c_write_byte error2: risr %08x\n",
445 i2c_regs->risr);
446 return -1;
447 }
448
449
450 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
451
452
453 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
454
455 return 0;
456}
457
458
459
460
461
462int i2c_probe(uchar chip)
463{
464 u32 mcr = 0;
465 struct u8500_i2c_regs *i2c_regs;
466
467 if (chip == CONFIG_SYS_I2C_SLAVE)
468 return 1;
469
470 i2c_regs = i2c_dev[i2c_bus_num];
471
472
473 WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
474
475
476 WRITE_FIELD(mcr, U8500_I2C_MCR_A10, U8500_I2C_MCR_SHIFT_A7, chip);
477
478
479 mcr |= U8500_I2C_MCR_OP;
480
481
482 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
483
484
485 mcr |= U8500_I2C_MCR_STOP;
486
487
488 writel(mcr, &i2c_regs->mcr);
489
490
491 if (loop_till_bit_clear((void *)&i2c_regs->risr,
492 U8500_I2C_INT_RXFE,
493 U8500_I2C_ENDAD_COUNTER)) {
494 i2c_abort(i2c_regs);
495 return -1;
496 }
497
498 flush_fifo(i2c_regs);
499
500
501 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
502
503
504 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
505
506 return 0;
507}
508
509
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513
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515
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517
518
519
520
521int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
522{
523 int i;
524 int rc;
525 struct u8500_i2c_regs *i2c_regs;
526
527 if (alen > 2) {
528 debug("I2C read: addr len %d not supported\n", alen);
529 return 1;
530 }
531
532 i2c_regs = i2c_dev[i2c_bus_num];
533
534 for (i = 0; i < len; i++) {
535 rc = i2c_read_byte(i2c_regs, chip, addr + i, alen, &buffer[i]);
536 if (rc != 0) {
537 debug("I2C read: I/O error: %d\n", rc);
538 i2c_abort(i2c_regs);
539 return rc;
540 }
541 }
542
543 return 0;
544}
545
546int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
547{
548 int rc;
549 struct u8500_i2c_regs *i2c_regs;
550 i2c_regs = i2c_dev[i2c_bus_num];
551
552 rc = __i2c_write(i2c_regs, chip, addr, alen, buffer,
553 len);
554 if (rc != 0) {
555 debug("I2C write: I/O error\n");
556 i2c_abort(i2c_regs);
557 return rc;
558 }
559 return 0;
560}
561
562int i2c_set_bus_num(unsigned int bus)
563{
564 if (bus > ARRAY_SIZE(i2c_dev) - 1) {
565 debug("i2c_set_bus_num: only up to bus %d supported\n",
566 ARRAY_SIZE(i2c_dev)-1);
567 return -1;
568 }
569
570 i2c_bus_num = bus;
571
572 if (!bus_initialized[i2c_bus_num])
573 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
574
575 return 0;
576}
577
578int i2c_set_bus_speed(unsigned int speed)
579{
580
581 if (speed > U8500_I2C_MAX_STANDARD_SCL) {
582 debug("i2c_set_bus_speed: only up to %d supported\n",
583 U8500_I2C_MAX_STANDARD_SCL);
584 return -1;
585 }
586
587
588 i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
589
590 return 0;
591}
592
593unsigned int i2c_get_bus_num(void)
594{
595 return i2c_bus_num;
596}
597
598unsigned int i2c_get_bus_speed(void)
599{
600 return i2c_bus_speed[i2c_bus_num];
601}
602