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25#include <config.h>
26#include <common.h>
27#include <malloc.h>
28#include <mmc.h>
29#include <part.h>
30#include <i2c.h>
31#include <twl4030.h>
32#include <twl6030.h>
33#include <palmas.h>
34#include <asm/gpio.h>
35#include <asm/io.h>
36#include <asm/arch/mmc_host_def.h>
37#include <asm/arch/sys_proto.h>
38
39
40#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
41 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
42#define OMAP_HSMMC_USE_GPIO
43#else
44#undef OMAP_HSMMC_USE_GPIO
45#endif
46
47
48#define SYSCTL_SRC (1 << 25)
49#define SYSCTL_SRD (1 << 26)
50
51struct omap_hsmmc_data {
52 struct hsmmc *base_addr;
53 struct mmc_config cfg;
54#ifdef OMAP_HSMMC_USE_GPIO
55 int cd_gpio;
56 int wp_gpio;
57#endif
58};
59
60
61#define MAX_RETRY_MS 1000
62
63static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
64static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
65 unsigned int siz);
66
67#ifdef OMAP_HSMMC_USE_GPIO
68static int omap_mmc_setup_gpio_in(int gpio, const char *label)
69{
70 int ret;
71
72#ifndef CONFIG_DM_GPIO
73 if (!gpio_is_valid(gpio))
74 return -1;
75#endif
76 ret = gpio_request(gpio, label);
77 if (ret)
78 return ret;
79
80 ret = gpio_direction_input(gpio);
81 if (ret)
82 return ret;
83
84 return gpio;
85}
86#endif
87
88#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
89static void omap4_vmmc_pbias_config(struct mmc *mmc)
90{
91 u32 value = 0;
92
93 value = readl((*ctrl)->control_pbiaslite);
94 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
95 writel(value, (*ctrl)->control_pbiaslite);
96
97 twl6030_power_mmc_init();
98 value = readl((*ctrl)->control_pbiaslite);
99 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
100 writel(value, (*ctrl)->control_pbiaslite);
101}
102#endif
103
104#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
105static void omap5_pbias_config(struct mmc *mmc)
106{
107 u32 value = 0;
108
109 value = readl((*ctrl)->control_pbias);
110 value &= ~SDCARD_PWRDNZ;
111 writel(value, (*ctrl)->control_pbias);
112 udelay(10);
113 value &= ~SDCARD_BIAS_PWRDNZ;
114 writel(value, (*ctrl)->control_pbias);
115
116 palmas_mmc1_poweron_ldo();
117
118 value = readl((*ctrl)->control_pbias);
119 value |= SDCARD_BIAS_PWRDNZ;
120 writel(value, (*ctrl)->control_pbias);
121 udelay(150);
122 value |= SDCARD_PWRDNZ;
123 writel(value, (*ctrl)->control_pbias);
124 udelay(150);
125}
126#endif
127
128static unsigned char mmc_board_init(struct mmc *mmc)
129{
130#if defined(CONFIG_OMAP34XX)
131 t2_t *t2_base = (t2_t *)T2_BASE;
132 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
133 u32 pbias_lite;
134
135 pbias_lite = readl(&t2_base->pbias_lite);
136 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
137#ifdef CONFIG_TARGET_OMAP3_CAIRO
138
139 pbias_lite &= ~PBIASLITEVMODE0;
140#endif
141 writel(pbias_lite, &t2_base->pbias_lite);
142
143 writel(pbias_lite | PBIASLITEPWRDNZ1 |
144 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
145 &t2_base->pbias_lite);
146
147 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
148 &t2_base->devconf0);
149
150 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
151 &t2_base->devconf1);
152
153
154 if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
155 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
156 &t2_base->ctl_prog_io1);
157
158 writel(readl(&prcm_base->fclken1_core) |
159 EN_MMC1 | EN_MMC2 | EN_MMC3,
160 &prcm_base->fclken1_core);
161
162 writel(readl(&prcm_base->iclken1_core) |
163 EN_MMC1 | EN_MMC2 | EN_MMC3,
164 &prcm_base->iclken1_core);
165#endif
166
167#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
168
169 if (mmc->block_dev.dev == 0)
170 omap4_vmmc_pbias_config(mmc);
171#endif
172#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
173 if (mmc->block_dev.dev == 0)
174 omap5_pbias_config(mmc);
175#endif
176
177 return 0;
178}
179
180void mmc_init_stream(struct hsmmc *mmc_base)
181{
182 ulong start;
183
184 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
185
186 writel(MMC_CMD0, &mmc_base->cmd);
187 start = get_timer(0);
188 while (!(readl(&mmc_base->stat) & CC_MASK)) {
189 if (get_timer(0) - start > MAX_RETRY_MS) {
190 printf("%s: timedout waiting for cc!\n", __func__);
191 return;
192 }
193 }
194 writel(CC_MASK, &mmc_base->stat)
195 ;
196 writel(MMC_CMD0, &mmc_base->cmd)
197 ;
198 start = get_timer(0);
199 while (!(readl(&mmc_base->stat) & CC_MASK)) {
200 if (get_timer(0) - start > MAX_RETRY_MS) {
201 printf("%s: timedout waiting for cc2!\n", __func__);
202 return;
203 }
204 }
205 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
206}
207
208
209static int omap_hsmmc_init_setup(struct mmc *mmc)
210{
211 struct hsmmc *mmc_base;
212 unsigned int reg_val;
213 unsigned int dsor;
214 ulong start;
215
216 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
217 mmc_board_init(mmc);
218
219 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
220 &mmc_base->sysconfig);
221 start = get_timer(0);
222 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
223 if (get_timer(0) - start > MAX_RETRY_MS) {
224 printf("%s: timedout waiting for cc2!\n", __func__);
225 return TIMEOUT;
226 }
227 }
228 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
229 start = get_timer(0);
230 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
231 if (get_timer(0) - start > MAX_RETRY_MS) {
232 printf("%s: timedout waiting for softresetall!\n",
233 __func__);
234 return TIMEOUT;
235 }
236 }
237 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
238 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
239 &mmc_base->capa);
240
241 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
242
243 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
244 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
245 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
246
247 dsor = 240;
248 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
249 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
250 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
251 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
252 start = get_timer(0);
253 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
254 if (get_timer(0) - start > MAX_RETRY_MS) {
255 printf("%s: timedout waiting for ics!\n", __func__);
256 return TIMEOUT;
257 }
258 }
259 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
260
261 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
262
263 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
264 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
265 &mmc_base->ie);
266
267 mmc_init_stream(mmc_base);
268
269 return 0;
270}
271
272
273
274
275
276
277
278static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
279{
280 ulong start;
281
282 mmc_reg_out(&mmc_base->sysctl, bit, bit);
283
284
285
286
287
288
289
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292
293
294
295
296
297
298#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
299 defined(CONFIG_AM33XX)
300 if (!(readl(&mmc_base->sysctl) & bit)) {
301 start = get_timer(0);
302 while (!(readl(&mmc_base->sysctl) & bit)) {
303 if (get_timer(0) - start > MAX_RETRY_MS)
304 return;
305 }
306 }
307#endif
308 start = get_timer(0);
309 while ((readl(&mmc_base->sysctl) & bit) != 0) {
310 if (get_timer(0) - start > MAX_RETRY_MS) {
311 printf("%s: timedout waiting for sysctl %x to clear\n",
312 __func__, bit);
313 return;
314 }
315 }
316}
317
318static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
319 struct mmc_data *data)
320{
321 struct hsmmc *mmc_base;
322 unsigned int flags, mmc_stat;
323 ulong start;
324
325 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
326 start = get_timer(0);
327 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
328 if (get_timer(0) - start > MAX_RETRY_MS) {
329 printf("%s: timedout waiting on cmd inhibit to clear\n",
330 __func__);
331 return TIMEOUT;
332 }
333 }
334 writel(0xFFFFFFFF, &mmc_base->stat);
335 start = get_timer(0);
336 while (readl(&mmc_base->stat)) {
337 if (get_timer(0) - start > MAX_RETRY_MS) {
338 printf("%s: timedout waiting for STAT (%x) to clear\n",
339 __func__, readl(&mmc_base->stat));
340 return TIMEOUT;
341 }
342 }
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
359 udelay(50000);
360
361 if (!(cmd->resp_type & MMC_RSP_PRESENT))
362 flags = 0;
363 else if (cmd->resp_type & MMC_RSP_136)
364 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
365 else if (cmd->resp_type & MMC_RSP_BUSY)
366 flags = RSP_TYPE_LGHT48B;
367 else
368 flags = RSP_TYPE_LGHT48;
369
370
371 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
372 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
373
374 if (cmd->resp_type & MMC_RSP_CRC)
375 flags |= CCCE_CHECK;
376 if (cmd->resp_type & MMC_RSP_OPCODE)
377 flags |= CICE_CHECK;
378
379 if (data) {
380 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
381 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
382 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
383 data->blocksize = 512;
384 writel(data->blocksize | (data->blocks << 16),
385 &mmc_base->blk);
386 } else
387 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
388
389 if (data->flags & MMC_DATA_READ)
390 flags |= (DP_DATA | DDIR_READ);
391 else
392 flags |= (DP_DATA | DDIR_WRITE);
393 }
394
395 writel(cmd->cmdarg, &mmc_base->arg);
396 udelay(20);
397 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
398
399 start = get_timer(0);
400 do {
401 mmc_stat = readl(&mmc_base->stat);
402 if (get_timer(0) - start > MAX_RETRY_MS) {
403 printf("%s : timeout: No status update\n", __func__);
404 return TIMEOUT;
405 }
406 } while (!mmc_stat);
407
408 if ((mmc_stat & IE_CTO) != 0) {
409 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
410 return TIMEOUT;
411 } else if ((mmc_stat & ERRI_MASK) != 0)
412 return -1;
413
414 if (mmc_stat & CC_MASK) {
415 writel(CC_MASK, &mmc_base->stat);
416 if (cmd->resp_type & MMC_RSP_PRESENT) {
417 if (cmd->resp_type & MMC_RSP_136) {
418
419 cmd->response[3] = readl(&mmc_base->rsp10);
420 cmd->response[2] = readl(&mmc_base->rsp32);
421 cmd->response[1] = readl(&mmc_base->rsp54);
422 cmd->response[0] = readl(&mmc_base->rsp76);
423 } else
424
425 cmd->response[0] = readl(&mmc_base->rsp10);
426 }
427 }
428
429 if (data && (data->flags & MMC_DATA_READ)) {
430 mmc_read_data(mmc_base, data->dest,
431 data->blocksize * data->blocks);
432 } else if (data && (data->flags & MMC_DATA_WRITE)) {
433 mmc_write_data(mmc_base, data->src,
434 data->blocksize * data->blocks);
435 }
436 return 0;
437}
438
439static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
440{
441 unsigned int *output_buf = (unsigned int *)buf;
442 unsigned int mmc_stat;
443 unsigned int count;
444
445
446
447
448 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
449 count /= 4;
450
451 while (size) {
452 ulong start = get_timer(0);
453 do {
454 mmc_stat = readl(&mmc_base->stat);
455 if (get_timer(0) - start > MAX_RETRY_MS) {
456 printf("%s: timedout waiting for status!\n",
457 __func__);
458 return TIMEOUT;
459 }
460 } while (mmc_stat == 0);
461
462 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
463 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
464
465 if ((mmc_stat & ERRI_MASK) != 0)
466 return 1;
467
468 if (mmc_stat & BRR_MASK) {
469 unsigned int k;
470
471 writel(readl(&mmc_base->stat) | BRR_MASK,
472 &mmc_base->stat);
473 for (k = 0; k < count; k++) {
474 *output_buf = readl(&mmc_base->data);
475 output_buf++;
476 }
477 size -= (count*4);
478 }
479
480 if (mmc_stat & BWR_MASK)
481 writel(readl(&mmc_base->stat) | BWR_MASK,
482 &mmc_base->stat);
483
484 if (mmc_stat & TC_MASK) {
485 writel(readl(&mmc_base->stat) | TC_MASK,
486 &mmc_base->stat);
487 break;
488 }
489 }
490 return 0;
491}
492
493static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
494 unsigned int size)
495{
496 unsigned int *input_buf = (unsigned int *)buf;
497 unsigned int mmc_stat;
498 unsigned int count;
499
500
501
502
503 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
504 count /= 4;
505
506 while (size) {
507 ulong start = get_timer(0);
508 do {
509 mmc_stat = readl(&mmc_base->stat);
510 if (get_timer(0) - start > MAX_RETRY_MS) {
511 printf("%s: timedout waiting for status!\n",
512 __func__);
513 return TIMEOUT;
514 }
515 } while (mmc_stat == 0);
516
517 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
518 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
519
520 if ((mmc_stat & ERRI_MASK) != 0)
521 return 1;
522
523 if (mmc_stat & BWR_MASK) {
524 unsigned int k;
525
526 writel(readl(&mmc_base->stat) | BWR_MASK,
527 &mmc_base->stat);
528 for (k = 0; k < count; k++) {
529 writel(*input_buf, &mmc_base->data);
530 input_buf++;
531 }
532 size -= (count*4);
533 }
534
535 if (mmc_stat & BRR_MASK)
536 writel(readl(&mmc_base->stat) | BRR_MASK,
537 &mmc_base->stat);
538
539 if (mmc_stat & TC_MASK) {
540 writel(readl(&mmc_base->stat) | TC_MASK,
541 &mmc_base->stat);
542 break;
543 }
544 }
545 return 0;
546}
547
548static void omap_hsmmc_set_ios(struct mmc *mmc)
549{
550 struct hsmmc *mmc_base;
551 unsigned int dsor = 0;
552 ulong start;
553
554 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
555
556 switch (mmc->bus_width) {
557 case 8:
558 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
559 &mmc_base->con);
560 break;
561
562 case 4:
563 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
564 &mmc_base->con);
565 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
566 &mmc_base->hctl);
567 break;
568
569 case 1:
570 default:
571 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
572 &mmc_base->con);
573 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
574 &mmc_base->hctl);
575 break;
576 }
577
578
579
580 if (mmc->clock != 0) {
581 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
582 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
583 dsor++;
584 }
585
586 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
587 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
588
589 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
590 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
591
592 start = get_timer(0);
593 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
594 if (get_timer(0) - start > MAX_RETRY_MS) {
595 printf("%s: timedout waiting for ics!\n", __func__);
596 return;
597 }
598 }
599 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
600}
601
602#ifdef OMAP_HSMMC_USE_GPIO
603static int omap_hsmmc_getcd(struct mmc *mmc)
604{
605 struct omap_hsmmc_data *priv_data = mmc->priv;
606 int cd_gpio;
607
608
609 cd_gpio = priv_data->cd_gpio;
610 if (cd_gpio < 0)
611 return 1;
612
613
614 return !gpio_get_value(cd_gpio);
615}
616
617static int omap_hsmmc_getwp(struct mmc *mmc)
618{
619 struct omap_hsmmc_data *priv_data = mmc->priv;
620 int wp_gpio;
621
622
623 wp_gpio = priv_data->wp_gpio;
624 if (wp_gpio < 0)
625 return 0;
626
627
628 return gpio_get_value(wp_gpio);
629}
630#endif
631
632static const struct mmc_ops omap_hsmmc_ops = {
633 .send_cmd = omap_hsmmc_send_cmd,
634 .set_ios = omap_hsmmc_set_ios,
635 .init = omap_hsmmc_init_setup,
636#ifdef OMAP_HSMMC_USE_GPIO
637 .getcd = omap_hsmmc_getcd,
638 .getwp = omap_hsmmc_getwp,
639#endif
640};
641
642int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
643 int wp_gpio)
644{
645 struct mmc *mmc;
646 struct omap_hsmmc_data *priv_data;
647 struct mmc_config *cfg;
648 uint host_caps_val;
649
650 priv_data = malloc(sizeof(*priv_data));
651 if (priv_data == NULL)
652 return -1;
653
654 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
655 MMC_MODE_HC;
656
657 switch (dev_index) {
658 case 0:
659 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
660 break;
661#ifdef OMAP_HSMMC2_BASE
662 case 1:
663 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
664#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
665 defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && \
666 defined(CONFIG_HSMMC2_8BIT)
667
668 host_caps_val |= MMC_MODE_8BIT;
669#endif
670 break;
671#endif
672#ifdef OMAP_HSMMC3_BASE
673 case 2:
674 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
675#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
676
677 host_caps_val |= MMC_MODE_8BIT;
678#endif
679 break;
680#endif
681 default:
682 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
683 return 1;
684 }
685#ifdef OMAP_HSMMC_USE_GPIO
686
687 priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
688 priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
689#endif
690
691 cfg = &priv_data->cfg;
692
693 cfg->name = "OMAP SD/MMC";
694 cfg->ops = &omap_hsmmc_ops;
695
696 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
697 cfg->host_caps = host_caps_val & ~host_caps_mask;
698
699 cfg->f_min = 400000;
700
701 if (f_max != 0)
702 cfg->f_max = f_max;
703 else {
704 if (cfg->host_caps & MMC_MODE_HS) {
705 if (cfg->host_caps & MMC_MODE_HS_52MHz)
706 cfg->f_max = 52000000;
707 else
708 cfg->f_max = 26000000;
709 } else
710 cfg->f_max = 20000000;
711 }
712
713 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
714
715#if defined(CONFIG_OMAP34XX)
716
717
718
719 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
720 cfg->b_max = 1;
721#endif
722 mmc = mmc_create(cfg, priv_data);
723 if (mmc == NULL)
724 return -1;
725
726 return 0;
727}
728
