1
2
3
4
5#include <dm/platform_data/serial_sh.h>
6
7struct uart_port {
8 unsigned long iobase;
9 unsigned char *membase;
10 unsigned long mapbase;
11 enum sh_serial_type type;
12 enum sh_clk_mode clk_mode;
13};
14
15#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
16#include <asm/regs306x.h>
17#endif
18#if defined(CONFIG_H8S2678)
19#include <asm/regs267x.h>
20#endif
21
22#if defined(CONFIG_CPU_SH7706) || \
23 defined(CONFIG_CPU_SH7707) || \
24 defined(CONFIG_CPU_SH7708) || \
25 defined(CONFIG_CPU_SH7709)
26# define SCPCR 0xA4000116
27# define SCPDR 0xA4000136
28# define SCSCR_INIT(port) 0x30
29#elif defined(CONFIG_CPU_SH7705)
30# define SCIF0 0xA4400000
31# define SCIF2 0xA4410000
32# define SCSMR_Ir 0xA44A0000
33# define IRDA_SCIF SCIF0
34# define SCPCR 0xA4000116
35# define SCPDR 0xA4000136
36
37
38
39
40
41# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
42#elif defined(CONFIG_CPU_SH7720) || \
43 defined(CONFIG_CPU_SH7721) || \
44 defined(CONFIG_ARCH_SH7367) || \
45 defined(CONFIG_ARCH_SH7377) || \
46 defined(CONFIG_ARCH_SH7372) || \
47 defined(CONFIG_SH73A0) || \
48 defined(CONFIG_R8A7740)
49# define SCSCR_INIT(port) 0x0030
50# define PORT_PTCR 0xA405011EUL
51# define PORT_PVCR 0xA4050122UL
52# define SCIF_ORER 0x0200
53#elif defined(CONFIG_SH_RTS7751R2D)
54# define SCSPTR1 0xFFE0001C
55# define SCSPTR2 0xFFE80020
56# define SCIF_ORER 0x0001
57# define SCSCR_INIT(port) 0x3a
58#elif defined(CONFIG_CPU_SH7750) || \
59 defined(CONFIG_CPU_SH7750R) || \
60 defined(CONFIG_CPU_SH7750S) || \
61 defined(CONFIG_CPU_SH7091) || \
62 defined(CONFIG_CPU_SH7751) || \
63 defined(CONFIG_CPU_SH7751R)
64# define SCSPTR1 0xffe0001c
65# define SCSPTR2 0xFFE80020
66# define SCIF_ORER 0x0001
67# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
68 0x30 : \
69 0x38 )
70#elif defined(CONFIG_CPU_SH7760)
71# define SCSPTR0 0xfe600024
72# define SCSPTR1 0xfe610024
73# define SCSPTR2 0xfe620024
74# define SCIF_ORER 0x0001
75# define SCSCR_INIT(port) 0x38
76#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
77# define SCSPTR0 0xA4400000
78# define SCIF_ORER 0x0001
79# define PACR 0xa4050100
80# define PBCR 0xa4050102
81# define SCSCR_INIT(port) 0x3B
82#elif defined(CONFIG_CPU_SH7343)
83# define SCSPTR0 0xffe00010
84# define SCSPTR1 0xffe10010
85# define SCSPTR2 0xffe20010
86# define SCSPTR3 0xffe30010
87# define SCSCR_INIT(port) 0x32
88#elif defined(CONFIG_CPU_SH7722)
89# define PADR 0xA4050120
90# undef PSDR
91# define PSDR 0xA405013e
92# define PWDR 0xA4050166
93# define PSCR 0xA405011E
94# define SCIF_ORER 0x0001
95# define SCSCR_INIT(port) 0x0038
96#elif defined(CONFIG_CPU_SH7366)
97# define SCPDR0 0xA405013E
98# define SCSPTR0 SCPDR0
99# define SCIF_ORER 0x0001
100# define SCSCR_INIT(port) 0x0038
101#elif defined(CONFIG_CPU_SH7723)
102# define SCSPTR0 0xa4050160
103# define SCSPTR1 0xa405013e
104# define SCSPTR2 0xa4050160
105# define SCSPTR3 0xa405013e
106# define SCSPTR4 0xa4050128
107# define SCSPTR5 0xa4050128
108# define SCIF_ORER 0x0001
109# define SCSCR_INIT(port) 0x0038
110#elif defined(CONFIG_CPU_SH7724)
111# define SCIF_ORER 0x0001
112# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
113 0x30 : \
114 0x38 )
115#elif defined(CONFIG_CPU_SH7734)
116# define SCSPTR0 0xFFE40020
117# define SCSPTR1 0xFFE41020
118# define SCSPTR2 0xFFE42020
119# define SCSPTR3 0xFFE43020
120# define SCSPTR4 0xFFE44020
121# define SCSPTR5 0xFFE45020
122# define SCIF_ORER 0x0001
123# define SCSCR_INIT(port) 0x0038
124#elif defined(CONFIG_CPU_SH4_202)
125# define SCSPTR2 0xffe80020
126# define SCIF_ORER 0x0001
127# define SCSCR_INIT(port) 0x38
128#elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
129# define SCIF_BASE_ADDR 0x01030000
130# define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
131# define SCIF_PTR2_OFFS 0x0000020
132# define SCIF_LSR2_OFFS 0x0000024
133# define SCSPTR\
134 ((port->mapbase)+SCIF_PTR2_OFFS)
135# define SCLSR2\
136 ((port->mapbase)+SCIF_LSR2_OFFS)
137# define SCSCR_INIT(port) 0x38
138#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
139# define SCSCR_INIT(port) 0x30
140# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
141#elif defined(CONFIG_H8S2678)
142# define SCSCR_INIT(port) 0x30
143# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
144#elif defined(CONFIG_CPU_SH7757) || \
145 defined(CONFIG_CPU_SH7752) || \
146 defined(CONFIG_CPU_SH7753)
147# define SCSPTR0 0xfe4b0020
148# define SCSPTR1 0xfe4b0020
149# define SCSPTR2 0xfe4b0020
150# define SCIF_ORER 0x0001
151# define SCSCR_INIT(port) 0x38
152# define SCIF_ONLY
153#elif defined(CONFIG_CPU_SH7763)
154# define SCSPTR0 0xffe00024
155# define SCSPTR1 0xffe08024
156# define SCSPTR2 0xffe10020
157# define SCIF_ORER 0x0001
158# define SCSCR_INIT(port) 0x38
159#elif defined(CONFIG_CPU_SH7770)
160# define SCSPTR0 0xff923020
161# define SCSPTR1 0xff924020
162# define SCSPTR2 0xff925020
163# define SCIF_ORER 0x0001
164# define SCSCR_INIT(port) 0x3c
165#elif defined(CONFIG_CPU_SH7780)
166# define SCSPTR0 0xffe00024
167# define SCSPTR1 0xffe10024
168# define SCIF_ORER 0x0001
169
170#if defined(CONFIG_SH_SH2007)
171
172# define SCSCR_INIT(port) 0x38
173#else
174
175# define SCSCR_INIT(port) 0x3a
176#endif
177
178#elif defined(CONFIG_CPU_SH7785) || \
179 defined(CONFIG_CPU_SH7786)
180# define SCSPTR0 0xffea0024
181# define SCSPTR1 0xffeb0024
182# define SCSPTR2 0xffec0024
183# define SCSPTR3 0xffed0024
184# define SCSPTR4 0xffee0024
185# define SCSPTR5 0xffef0024
186# define SCIF_ORER 0x0001
187# define SCSCR_INIT(port) 0x3a
188#elif defined(CONFIG_CPU_SH7201) || \
189 defined(CONFIG_CPU_SH7203) || \
190 defined(CONFIG_CPU_SH7206) || \
191 defined(CONFIG_CPU_SH7263) || \
192 defined(CONFIG_CPU_SH7264)
193# define SCSPTR0 0xfffe8020
194# define SCSPTR1 0xfffe8820
195# define SCSPTR2 0xfffe9020
196# define SCSPTR3 0xfffe9820
197# if defined(CONFIG_CPU_SH7201)
198# define SCSPTR4 0xfffeA020
199# define SCSPTR5 0xfffeA820
200# define SCSPTR6 0xfffeB020
201# define SCSPTR7 0xfffeB820
202# endif
203# define SCSCR_INIT(port) 0x38
204#elif defined(CONFIG_CPU_SH7269)
205# define SCSPTR0 0xe8007020
206# define SCSPTR1 0xe8007820
207# define SCSPTR2 0xe8008020
208# define SCSPTR3 0xe8008820
209# define SCSPTR4 0xe8009020
210# define SCSPTR5 0xe8009820
211# define SCSPTR6 0xe800a020
212# define SCSPTR7 0xe800a820
213# define SCSCR_INIT(port) 0x38
214#elif defined(CONFIG_CPU_SH7619)
215# define SCSPTR0 0xf8400020
216# define SCSPTR1 0xf8410020
217# define SCSPTR2 0xf8420020
218# define SCIF_ORER 0x0001
219# define SCSCR_INIT(port) 0x38
220#elif defined(CONFIG_CPU_SHX3)
221# define SCSPTR0 0xffc30020
222# define SCSPTR1 0xffc40020
223# define SCSPTR2 0xffc50020
224# define SCSPTR3 0xffc60020
225# define SCIF_ORER 0x0001
226# define SCSCR_INIT(port) 0x38
227#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
228 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
229# define SCIF_ORER 0x0001
230# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
231
232#else
233# error CPU subtype not defined
234#endif
235
236
237#define SCI_CTRL_FLAGS_TIE 0x80
238#define SCI_CTRL_FLAGS_RIE 0x40
239#define SCI_CTRL_FLAGS_TE 0x20
240#define SCI_CTRL_FLAGS_RE 0x10
241#if defined(CONFIG_CPU_SH7750) || \
242 defined(CONFIG_CPU_SH7091) || \
243 defined(CONFIG_CPU_SH7750R) || \
244 defined(CONFIG_CPU_SH7722) || \
245 defined(CONFIG_CPU_SH7734) || \
246 defined(CONFIG_CPU_SH7750S) || \
247 defined(CONFIG_CPU_SH7751) || \
248 defined(CONFIG_CPU_SH7751R) || \
249 defined(CONFIG_CPU_SH7763) || \
250 defined(CONFIG_CPU_SH7780) || \
251 defined(CONFIG_CPU_SH7785) || \
252 defined(CONFIG_CPU_SH7786) || \
253 defined(CONFIG_CPU_SHX3)
254#define SCI_CTRL_FLAGS_REIE 0x08
255#elif defined(CONFIG_CPU_SH7724)
256#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
257#else
258#define SCI_CTRL_FLAGS_REIE 0
259#endif
260
261
262
263
264
265
266#define SCI_TDRE 0x80
267#define SCI_RDRF 0x40
268#define SCI_ORER 0x20
269#define SCI_FER 0x10
270#define SCI_PER 0x08
271#define SCI_TEND 0x04
272
273
274
275#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
276
277
278#define SCIF_ER 0x0080
279#define SCIF_TEND 0x0040
280#define SCIF_TDFE 0x0020
281#define SCIF_BRK 0x0010
282#define SCIF_FER 0x0008
283#define SCIF_PER 0x0004
284#define SCIF_RDF 0x0002
285#define SCIF_DR 0x0001
286
287#if defined(CONFIG_CPU_SH7705) || \
288 defined(CONFIG_CPU_SH7720) || \
289 defined(CONFIG_CPU_SH7721) || \
290 defined(CONFIG_ARCH_SH7367) || \
291 defined(CONFIG_ARCH_SH7377) || \
292 defined(CONFIG_ARCH_SH7372) || \
293 defined(CONFIG_SH73A0) || \
294 defined(CONFIG_R8A7740)
295# define SCIF_ORER 0x0200
296# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
297# define SCIF_RFDC_MASK 0x007f
298# define SCIF_TXROOM_MAX 64
299#elif defined(CONFIG_CPU_SH7763)
300# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
301# define SCIF_RFDC_MASK 0x007f
302# define SCIF_TXROOM_MAX 64
303
304# define SCIF2_RFDC_MASK 0x001f
305# define SCIF2_TXROOM_MAX 16
306#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
307 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
308# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
309# define SCIF_RFDC_MASK 0x003f
310#else
311# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
312# define SCIF_RFDC_MASK 0x001f
313# define SCIF_TXROOM_MAX 16
314#endif
315
316#ifndef SCIF_ORER
317#define SCIF_ORER 0x0000
318#endif
319
320#define SCxSR_TEND(port)\
321 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
322#define SCxSR_ERRORS(port)\
323 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
324#define SCxSR_RDxF(port)\
325 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
326#define SCxSR_TDxE(port)\
327 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
328#define SCxSR_FER(port)\
329 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
330#define SCxSR_PER(port)\
331 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
332#define SCxSR_BRK(port)\
333 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
334#define SCxSR_ORER(port)\
335 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
336
337#if defined(CONFIG_CPU_SH7705) || \
338 defined(CONFIG_CPU_SH7720) || \
339 defined(CONFIG_CPU_SH7721) || \
340 defined(CONFIG_ARCH_SH7367) || \
341 defined(CONFIG_ARCH_SH7377) || \
342 defined(CONFIG_ARCH_SH7372) || \
343 defined(CONFIG_SH73A0) || \
344 defined(CONFIG_R8A7740)
345# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
346# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
347# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
348# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
349#else
350# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
351# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
352# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
353# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
354#endif
355
356
357#define SCFCR_RFRST 0x0002
358#define SCFCR_TFRST 0x0004
359#define SCFCR_TCRST 0x4000
360#define SCFCR_MCE 0x0008
361
362#define SCI_MAJOR 204
363#define SCI_MINOR_START 8
364
365
366#define SCI_RX_THROTTLE 0x0000001
367
368#define SCI_MAGIC 0xbabeface
369
370
371
372
373
374#define SCI_EVENT_WRITE_WAKEUP 0
375
376#define SCI_IN(size, offset)\
377 if ((size) == 8) {\
378 return readb(port->membase + (offset));\
379 } else {\
380 return readw(port->membase + (offset));\
381 }
382#define SCI_OUT(size, offset, value)\
383 if ((size) == 8) {\
384 writeb(value, port->membase + (offset));\
385 } else if ((size) == 16) {\
386 writew(value, port->membase + (offset));\
387 }
388
389#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
390 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
391 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
392 SCI_IN(scif_size, scif_offset)\
393 } else { \
394 SCI_IN(sci_size, sci_offset);\
395 }\
396 }\
397static inline void sci_##name##_out(struct uart_port *port,\
398 unsigned int value) {\
399 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
400 SCI_OUT(scif_size, scif_offset, value)\
401 } else { \
402 SCI_OUT(sci_size, sci_offset, value);\
403 }\
404}
405
406#ifdef CONFIG_H8300
407
408#define CPU_SCIF_FNS(name) \
409 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
410 return 0;\
411 }\
412 static inline void sci_##name##_out(struct uart_port *port,\
413 unsigned int value) {\
414 }
415#else
416#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
417 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
418 SCI_IN(scif_size, scif_offset);\
419 }\
420 static inline void sci_##name##_out(struct uart_port *port,\
421 unsigned int value) {\
422 SCI_OUT(scif_size, scif_offset, value);\
423 }
424#endif
425
426#define CPU_SCI_FNS(name, sci_offset, sci_size)\
427 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
428 SCI_IN(sci_size, sci_offset);\
429 }\
430 static inline void sci_##name##_out(struct uart_port *port,\
431 unsigned int value) {\
432 SCI_OUT(sci_size, sci_offset, value);\
433 }
434
435#if defined(CONFIG_CPU_SH3) || \
436 defined(CONFIG_ARCH_SH7367) || \
437 defined(CONFIG_ARCH_SH7377) || \
438 defined(CONFIG_ARCH_SH7372) || \
439 defined(CONFIG_SH73A0) || \
440 defined(CONFIG_R8A7740)
441#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
442#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
443 sh4_sci_offset, sh4_sci_size, \
444 sh3_scif_offset, sh3_scif_size, \
445 sh4_scif_offset, sh4_scif_size, \
446 h8_sci_offset, h8_sci_size) \
447 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
448 sh4_scif_offset, sh4_scif_size)
449#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
450 sh4_scif_offset, sh4_scif_size) \
451 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
452#elif defined(CONFIG_CPU_SH7705) || \
453 defined(CONFIG_CPU_SH7720) || \
454 defined(CONFIG_CPU_SH7721) || \
455 defined(CONFIG_ARCH_SH7367) || \
456 defined(CONFIG_ARCH_SH7377) || \
457 defined(CONFIG_SH73A0)
458#define SCIF_FNS(name, scif_offset, scif_size) \
459 CPU_SCIF_FNS(name, scif_offset, scif_size)
460#elif defined(CONFIG_ARCH_SH7372) || \
461 defined(CONFIG_R8A7740)
462#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
463 sh4_scifb_offset, sh4_scifb_size) \
464 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
465 sh4_scifb_offset, sh4_scifb_size)
466#define SCIF_FNS(name, scif_offset, scif_size) \
467 CPU_SCIF_FNS(name, scif_offset, scif_size)
468#else
469#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
470 sh4_sci_offset, sh4_sci_size, \
471 sh3_scif_offset, sh3_scif_size,\
472 sh4_scif_offset, sh4_scif_size, \
473 h8_sci_offset, h8_sci_size) \
474 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
475 sh3_scif_offset, sh3_scif_size)
476#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
477 sh4_scif_offset, sh4_scif_size) \
478 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
479#endif
480#elif defined(__H8300H__) || defined(__H8300S__)
481#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
482 sh4_sci_offset, sh4_sci_size, \
483 sh3_scif_offset, sh3_scif_size,\
484 sh4_scif_offset, sh4_scif_size, \
485 h8_sci_offset, h8_sci_size) \
486 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
487#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
488 sh4_scif_offset, sh4_scif_size) \
489 CPU_SCIF_FNS(name)
490#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
491 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
492 sh4_scif_offset, sh4_scif_size) \
493 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
494 sh4_scif_offset, sh4_scif_size)
495 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
496 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
497#else
498#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
499 sh4_sci_offset, sh4_sci_size, \
500 sh3_scif_offset, sh3_scif_size,\
501 sh4_scif_offset, sh4_scif_size, \
502 h8_sci_offset, h8_sci_size) \
503 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
504 sh4_scif_offset, sh4_scif_size)
505#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
506 sh4_scif_offset, sh4_scif_size) \
507 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
508#endif
509
510#if defined(CONFIG_CPU_SH7705) || \
511 defined(CONFIG_CPU_SH7720) || \
512 defined(CONFIG_CPU_SH7721) || \
513 defined(CONFIG_ARCH_SH7367) || \
514 defined(CONFIG_ARCH_SH7377) || \
515 defined(CONFIG_SH73A0)
516
517SCIF_FNS(SCSMR, 0x00, 16)
518SCIF_FNS(SCBRR, 0x04, 8)
519SCIF_FNS(SCSCR, 0x08, 16)
520SCIF_FNS(SCTDSR, 0x0c, 8)
521SCIF_FNS(SCFER, 0x10, 16)
522SCIF_FNS(SCxSR, 0x14, 16)
523SCIF_FNS(SCFCR, 0x18, 16)
524SCIF_FNS(SCFDR, 0x1c, 16)
525SCIF_FNS(SCxTDR, 0x20, 8)
526SCIF_FNS(SCxRDR, 0x24, 8)
527SCIF_FNS(SCLSR, 0x00, 0)
528SCIF_FNS(DL, 0x00, 0)
529#elif defined(CONFIG_ARCH_SH7372) || \
530 defined(CONFIG_R8A7740)
531SCIF_FNS(SCSMR, 0x00, 16)
532SCIF_FNS(SCBRR, 0x04, 8)
533SCIF_FNS(SCSCR, 0x08, 16)
534SCIF_FNS(SCTDSR, 0x0c, 16)
535SCIF_FNS(SCFER, 0x10, 16)
536SCIF_FNS(SCxSR, 0x14, 16)
537SCIF_FNS(SCFCR, 0x18, 16)
538SCIF_FNS(SCFDR, 0x1c, 16)
539SCIF_FNS(SCTFDR, 0x38, 16)
540SCIF_FNS(SCRFDR, 0x3c, 16)
541SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
542SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
543SCIF_FNS(SCLSR, 0x00, 0)
544SCIF_FNS(DL, 0x00, 0)
545#elif defined(CONFIG_CPU_SH7723) ||\
546 defined(CONFIG_CPU_SH7724)
547SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
548SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
549SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
550SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
551SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
552SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
553SCIx_FNS(SCSPTR, 0, 0, 0, 0)
554SCIF_FNS(SCTDSR, 0x0c, 8)
555SCIF_FNS(SCFER, 0x10, 16)
556SCIF_FNS(SCFCR, 0x18, 16)
557SCIF_FNS(SCFDR, 0x1c, 16)
558SCIF_FNS(SCLSR, 0x24, 16)
559SCIF_FNS(DL, 0x00, 0)
560#else
561
562
563SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
564SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
565SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
566SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
567SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
568SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
569SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
570#if defined(CONFIG_CPU_SH7760) || \
571 defined(CONFIG_CPU_SH7780) || \
572 defined(CONFIG_CPU_SH7785) || \
573 defined(CONFIG_CPU_SH7786)
574SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
575SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
576SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
577SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
578SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
579#elif defined(CONFIG_CPU_SH7763)
580SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
581SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
582SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
583SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
584SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
585SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
586SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
587#else
588
589SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
590#if defined(CONFIG_CPU_SH7722)
591SCIF_FNS(SCSPTR, 0, 0, 0, 0)
592#else
593SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
594#endif
595SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
596#endif
597#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
598 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
599SCIF_FNS(DL, 0, 0, 0x30, 16)
600SCIF_FNS(CKS, 0, 0, 0x34, 16)
601#else
602SCIF_FNS(DL, 0, 0, 0x0, 0)
603#endif
604#endif
605#define sci_in(port, reg) sci_##reg##_in(port)
606#define sci_out(port, reg, value) sci_##reg##_out(port, value)
607
608
609#if defined(__H8300H__) || defined(__H8300S__)
610static const struct __attribute__((packed)) {
611 int port;
612 unsigned short rx, tx;
613} h8300_sci_pins[] = {
614#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
615 {
616 .port = H8300_GPIO_P9,
617 .rx = H8300_GPIO_B2,
618 .tx = H8300_GPIO_B0,
619 },
620 {
621 .port = H8300_GPIO_P9,
622 .rx = H8300_GPIO_B3,
623 .tx = H8300_GPIO_B1,
624 },
625 {
626 .port = H8300_GPIO_PB,
627 .rx = H8300_GPIO_B7,
628 .tx = H8300_GPIO_B6,
629 }
630#elif defined(CONFIG_H8S2678)
631 {
632 .port = H8300_GPIO_P3,
633 .rx = H8300_GPIO_B2,
634 .tx = H8300_GPIO_B0,
635 },
636 {
637 .port = H8300_GPIO_P3,
638 .rx = H8300_GPIO_B3,
639 .tx = H8300_GPIO_B1,
640 },
641 {
642 .port = H8300_GPIO_P5,
643 .rx = H8300_GPIO_B1,
644 .tx = H8300_GPIO_B0,
645 }
646#endif
647};
648#endif
649
650#if defined(CONFIG_CPU_SH7706) || \
651 defined(CONFIG_CPU_SH7707) || \
652 defined(CONFIG_CPU_SH7708) || \
653 defined(CONFIG_CPU_SH7709)
654static inline int sci_rxd_in(struct uart_port *port)
655{
656 if (port->mapbase == 0xfffffe80)
657 return __raw_readb(SCPDR)&0x01 ? 1 : 0;
658 return 1;
659}
660#elif defined(CONFIG_CPU_SH7750) || \
661 defined(CONFIG_CPU_SH7751) || \
662 defined(CONFIG_CPU_SH7751R) || \
663 defined(CONFIG_CPU_SH7750R) || \
664 defined(CONFIG_CPU_SH7750S) || \
665 defined(CONFIG_CPU_SH7091)
666static inline int sci_rxd_in(struct uart_port *port)
667{
668 if (port->mapbase == 0xffe00000)
669 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0;
670 return 1;
671}
672#elif defined(__H8300H__) || defined(__H8300S__)
673static inline int sci_rxd_in(struct uart_port *port)
674{
675 int ch = (port->mapbase - SMR0) >> 3;
676 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
677}
678#else
679static inline int sci_rxd_in(struct uart_port *port)
680{
681 return 1;
682}
683#endif
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717#if (defined(CONFIG_CPU_SH7780) || \
718 defined(CONFIG_CPU_SH7785) || \
719 defined(CONFIG_CPU_SH7786)) && \
720 !defined(CONFIG_SH_SH2007)
721#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
722#elif defined(CONFIG_CPU_SH7705) || \
723 defined(CONFIG_CPU_SH7720) || \
724 defined(CONFIG_CPU_SH7721) || \
725 defined(CONFIG_ARCH_SH7367) || \
726 defined(CONFIG_ARCH_SH7377) || \
727 defined(CONFIG_ARCH_SH7372) || \
728 defined(CONFIG_SH73A0) || \
729 defined(CONFIG_R8A7740)
730#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
731#elif defined(CONFIG_CPU_SH7723) ||\
732 defined(CONFIG_CPU_SH7724)
733static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
734{
735 if (port->type == PORT_SCIF)
736 return (clk+16*bps)/(32*bps)-1;
737 else
738 return ((clk*2)+16*bps)/(16*bps)-1;
739}
740#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
741#elif defined(__H8300H__) || defined(__H8300S__)
742#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
743#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
744 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
745#define DL_VALUE(bps, clk) (clk / bps / 16)
746#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1)
747#else
748#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
749#endif
750
751#ifndef DL_VALUE
752#define DL_VALUE(bps, clk) 0
753#endif
754