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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13
14#define CONFIG_BOOKE 1
15#define CONFIG_E500 1
16#define CONFIG_MPC8569 1
17#define CONFIG_MPC8569MDS 1
18
19#define CONFIG_FSL_ELBC 1
20
21#define CONFIG_SYS_SRIO
22#define CONFIG_SRIO1
23
24#define CONFIG_PCI 1
25#define CONFIG_PCIE1 1
26#define CONFIG_FSL_PCI_INIT 1
27#define CONFIG_PCI_INDIRECT_BRIDGE 1
28#define CONFIG_FSL_PCIE_RESET 1
29#define CONFIG_SYS_PCI_64BIT 1
30#define CONFIG_QE
31#define CONFIG_ENV_OVERWRITE
32#define CONFIG_FSL_LAW 1
33
34#ifndef __ASSEMBLY__
35extern unsigned long get_clock_freq(void);
36#endif
37
38#define CONFIG_SYS_CLK_FREQ 66666666
39#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
40
41#ifdef CONFIG_ATM
42#define CONFIG_PQ_MDS_PIB
43#define CONFIG_PQ_MDS_PIB_ATM
44#endif
45
46
47
48
49#define CONFIG_L2_CACHE
50#define CONFIG_BTB
51
52#ifndef CONFIG_SYS_TEXT_BASE
53#define CONFIG_SYS_TEXT_BASE 0xfff80000
54#endif
55
56#ifndef CONFIG_SYS_MONITOR_BASE
57#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
58#endif
59
60
61
62
63#define CONFIG_ENABLE_36BIT_PHYS 1
64
65#define CONFIG_BOARD_EARLY_INIT_F 1
66#define CONFIG_BOARD_EARLY_INIT_R 1
67#define CONFIG_HWCONFIG
68
69#define CONFIG_SYS_MEMTEST_START 0x00200000
70#define CONFIG_SYS_MEMTEST_END 0x00400000
71
72
73
74
75#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
76#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
77#define CONFIG_SYS_L2_SIZE (512 << 10)
78#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
79
80#define CONFIG_SYS_CCSRBAR 0xe0000000
81#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
82
83#if defined(CONFIG_NAND_SPL)
84#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
85#endif
86
87
88#define CONFIG_SYS_FSL_DDR3
89#undef CONFIG_FSL_DDR_INTERACTIVE
90#define CONFIG_SPD_EEPROM
91#define CONFIG_DDR_SPD
92#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
93
94#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
95
96#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
97
98#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
99
100#define CONFIG_NUM_DDR_CONTROLLERS 1
101#define CONFIG_DIMM_SLOTS_PER_CTLR 1
102#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
103
104
105#define SPD_EEPROM_ADDRESS 0x51
106
107
108#define CONFIG_SYS_SDRAM_SIZE 1024
109#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
110#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
111#define CONFIG_SYS_DDR_TIMING_3 0x00020000
112#define CONFIG_SYS_DDR_TIMING_0 0x00330004
113#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
114#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
115#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
116#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
117#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
118#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
119#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
120#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
121#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
122#define CONFIG_SYS_DDR_TIMING_4 0x00220001
123#define CONFIG_SYS_DDR_TIMING_5 0x03402400
124#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
125#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
126#define CONFIG_SYS_DDR_CDR_1 0x80040000
127#define CONFIG_SYS_DDR_CDR_2 0x00000000
128#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
129#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
130#define CONFIG_SYS_DDR_CONTROL 0xc7000000
131#define CONFIG_SYS_DDR_CONTROL2 0x24400000
132
133#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
134#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
135#define CONFIG_SYS_DDR_SBE 0x00010000
136
137#undef CONFIG_CLOCKS_IN_MHZ
138
139
140
141
142
143#define CONFIG_SYS_FLASH_BASE 0xfe000000
144#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
145
146#define CONFIG_SYS_BCSR_BASE 0xf8000000
147#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
148
149
150#define CONFIG_FLASH_BR_PRELIM 0xfe000801
151#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
152
153
154#define CONFIG_SYS_BR1_PRELIM 0xf8000801
155#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
156
157
158#define CONFIG_SYS_BR4_PRELIM 0xf8008801
159#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
160
161
162#define CONFIG_SYS_BR5_PRELIM 0xf8010801
163#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
164
165#define CONFIG_SYS_MAX_FLASH_BANKS 1
166#define CONFIG_SYS_MAX_FLASH_SECT 512
167#undef CONFIG_SYS_FLASH_CHECKSUM
168#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
169#define CONFIG_SYS_FLASH_WRITE_TOUT 500
170
171#undef CONFIG_SYS_RAMBOOT
172
173#define CONFIG_FLASH_CFI_DRIVER
174#define CONFIG_SYS_FLASH_CFI
175#define CONFIG_SYS_FLASH_EMPTY_INFO
176
177
178#ifndef CONFIG_NAND_SPL
179#define CONFIG_SYS_NAND_BASE 0xFC000000
180#else
181#define CONFIG_SYS_NAND_BASE 0xFFF00000
182#endif
183
184
185#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
186#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
187#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
188#define CONFIG_SYS_NAND_U_BOOT_START \
189 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
190#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
191#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
192#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
193
194#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
195#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
196#define CONFIG_SYS_MAX_NAND_DEVICE 1
197#define CONFIG_CMD_NAND 1
198#define CONFIG_NAND_FSL_ELBC 1
199#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
200#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
201 | (2<<BR_DECC_SHIFT) \
202 | BR_PS_8 \
203 | BR_MS_FCM \
204 | BR_V)
205#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
206 | OR_FCM_CSCT \
207 | OR_FCM_CST \
208 | OR_FCM_CHT \
209 | OR_FCM_SCY_1 \
210 | OR_FCM_TRLX \
211 | OR_FCM_EHTR)
212
213#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
214#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
215#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM
216#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM
217
218#define CONFIG_SYS_LBC_LCRR 0x00000004
219#define CONFIG_SYS_LBC_LBCR 0x00040000
220#define CONFIG_SYS_LBC_LSRT 0x20000000
221#define CONFIG_SYS_LBC_MRTPR 0x00000000
222
223#define CONFIG_SYS_INIT_RAM_LOCK 1
224#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
225#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
226
227#define CONFIG_SYS_GBL_DATA_OFFSET \
228 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
229#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
230
231#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
232#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
233
234
235#define CONFIG_CONS_INDEX 1
236#define CONFIG_SYS_NS16550
237#define CONFIG_SYS_NS16550_SERIAL
238#define CONFIG_SYS_NS16550_REG_SIZE 1
239#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
240#ifdef CONFIG_NAND_SPL
241#define CONFIG_NS16550_MIN_FUNCTIONS
242#endif
243
244#define CONFIG_SYS_BAUDRATE_TABLE \
245 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
246
247#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
248#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
249
250
251#define CONFIG_SYS_HUSH_PARSER
252#ifdef CONFIG_SYS_HUSH_PARSER
253#endif
254
255
256#define CONFIG_OF_LIBFDT 1
257#define CONFIG_OF_BOARD_SETUP 1
258#define CONFIG_OF_STDOUT_VIA_ALIAS 1
259
260
261
262
263#define CONFIG_SYS_I2C
264#define CONFIG_SYS_I2C_FSL
265#define CONFIG_SYS_FSL_I2C_SPEED 400000
266#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
267#define CONFIG_SYS_FSL_I2C2_SPEED 400000
268#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
269#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
270#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
271#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
272
273
274
275
276#define CONFIG_ID_EEPROM
277#ifdef CONFIG_ID_EEPROM
278#define CONFIG_SYS_I2C_EEPROM_NXID
279#endif
280#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
281#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
282#define CONFIG_SYS_EEPROM_BUS_NUM 1
283
284#define PLPPAR1_I2C_BIT_MASK 0x0000000F
285#define PLPPAR1_I2C2_VAL 0x00000000
286#define PLPPAR1_ESDHC_VAL 0x0000000A
287#define PLPDIR1_I2C_BIT_MASK 0x0000000F
288#define PLPDIR1_I2C2_VAL 0x0000000F
289#define PLPDIR1_ESDHC_VAL 0x00000006
290#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
291#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
292#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
293#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
294
295
296
297
298
299#define CONFIG_SYS_PCIE1_NAME "Slot"
300#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
301#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
302#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
303#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
304#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
305#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
306#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
307#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
308
309#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
310#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
311#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
312#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
313
314#ifdef CONFIG_QE
315
316
317
318#define CONFIG_SYS_UCC_RGMII_MODE
319#undef CONFIG_SYS_UCC_RMII_MODE
320
321#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
322#define CONFIG_UEC_ETH
323#define CONFIG_ETHPRIME "UEC0"
324#define CONFIG_PHY_MODE_NEED_CHANGE
325
326#define CONFIG_UEC_ETH1
327#define CONFIG_HAS_ETH0
328
329#ifdef CONFIG_UEC_ETH1
330#define CONFIG_SYS_UEC1_UCC_NUM 0
331#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
332#if defined(CONFIG_SYS_UCC_RGMII_MODE)
333#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
334#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
335#define CONFIG_SYS_UEC1_PHY_ADDR 7
336#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
337#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
338#elif defined(CONFIG_SYS_UCC_RMII_MODE)
339#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
340#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
341#define CONFIG_SYS_UEC1_PHY_ADDR 8
342#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
343#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
344#endif
345#endif
346
347#define CONFIG_UEC_ETH2
348#define CONFIG_HAS_ETH1
349
350#ifdef CONFIG_UEC_ETH2
351#define CONFIG_SYS_UEC2_UCC_NUM 1
352#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
353#if defined(CONFIG_SYS_UCC_RGMII_MODE)
354#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
355#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
356#define CONFIG_SYS_UEC2_PHY_ADDR 1
357#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
358#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
359#elif defined(CONFIG_SYS_UCC_RMII_MODE)
360#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
361#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
362#define CONFIG_SYS_UEC2_PHY_ADDR 0x9
363#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
364#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
365#endif
366#endif
367
368#define CONFIG_UEC_ETH3
369#define CONFIG_HAS_ETH2
370
371#ifdef CONFIG_UEC_ETH3
372#define CONFIG_SYS_UEC3_UCC_NUM 2
373#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
374#if defined(CONFIG_SYS_UCC_RGMII_MODE)
375#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
376#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
377#define CONFIG_SYS_UEC3_PHY_ADDR 2
378#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
379#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
380#elif defined(CONFIG_SYS_UCC_RMII_MODE)
381#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16
382#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
383#define CONFIG_SYS_UEC3_PHY_ADDR 0xA
384#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
385#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
386#endif
387#endif
388
389#define CONFIG_UEC_ETH4
390#define CONFIG_HAS_ETH3
391
392#ifdef CONFIG_UEC_ETH4
393#define CONFIG_SYS_UEC4_UCC_NUM 3
394#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
395#if defined(CONFIG_SYS_UCC_RGMII_MODE)
396#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
397#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
398#define CONFIG_SYS_UEC4_PHY_ADDR 3
399#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
400#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
401#elif defined(CONFIG_SYS_UCC_RMII_MODE)
402#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16
403#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
404#define CONFIG_SYS_UEC4_PHY_ADDR 0xB
405#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
406#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
407#endif
408#endif
409
410#undef CONFIG_UEC_ETH6
411#define CONFIG_HAS_ETH5
412
413#ifdef CONFIG_UEC_ETH6
414#define CONFIG_SYS_UEC6_UCC_NUM 5
415#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
416#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
417#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
418#define CONFIG_SYS_UEC6_PHY_ADDR 4
419#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
420#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
421#endif
422
423#undef CONFIG_UEC_ETH8
424#define CONFIG_HAS_ETH7
425
426#ifdef CONFIG_UEC_ETH8
427#define CONFIG_SYS_UEC8_UCC_NUM 7
428#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
429#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
430#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
431#define CONFIG_SYS_UEC8_PHY_ADDR 6
432#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
433#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
434#endif
435
436#endif
437
438#if defined(CONFIG_PCI)
439
440#define CONFIG_PCI_PNP
441
442#undef CONFIG_EEPRO100
443#undef CONFIG_TULIP
444#define CONFIG_E1000
445
446#undef CONFIG_PCI_SCAN_SHOW
447
448#endif
449
450
451
452
453#if defined(CONFIG_SYS_RAMBOOT)
454#else
455#define CONFIG_ENV_IS_IN_FLASH 1
456#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
457#define CONFIG_ENV_SECT_SIZE 0x20000
458#define CONFIG_ENV_SIZE 0x2000
459#endif
460
461#define CONFIG_LOADS_ECHO 1
462#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
463
464
465#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
466#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
467
468
469
470
471#define CONFIG_BOOTP_BOOTFILESIZE
472#define CONFIG_BOOTP_BOOTPATH
473#define CONFIG_BOOTP_GATEWAY
474#define CONFIG_BOOTP_HOSTNAME
475
476
477
478
479
480#include <config_cmd_default.h>
481
482#define CONFIG_CMD_PING
483#define CONFIG_CMD_I2C
484#define CONFIG_CMD_MII
485#define CONFIG_CMD_ELF
486#define CONFIG_CMD_IRQ
487#define CONFIG_CMD_SETEXPR
488#define CONFIG_CMD_REGINFO
489
490#if defined(CONFIG_PCI)
491 #define CONFIG_CMD_PCI
492#endif
493
494
495#undef CONFIG_WATCHDOG
496
497#define CONFIG_MMC 1
498
499#ifdef CONFIG_MMC
500#define CONFIG_FSL_ESDHC
501#define CONFIG_FSL_ESDHC_PIN_MUX
502#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
503#define CONFIG_CMD_MMC
504#define CONFIG_GENERIC_MMC
505#define CONFIG_CMD_EXT2
506#define CONFIG_CMD_FAT
507#define CONFIG_DOS_PARTITION
508#endif
509
510
511
512
513#define CONFIG_SYS_LONGHELP
514#define CONFIG_CMDLINE_EDITING
515#define CONFIG_AUTO_COMPLETE
516#define CONFIG_SYS_LOAD_ADDR 0x2000000
517#if defined(CONFIG_CMD_KGDB)
518#define CONFIG_SYS_CBSIZE 2048
519#else
520#define CONFIG_SYS_CBSIZE 512
521#endif
522#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
523
524#define CONFIG_SYS_MAXARGS 32
525#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
526
527
528
529
530
531
532
533#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
534#define CONFIG_SYS_BOOTM_LEN (64 << 20)
535
536#if defined(CONFIG_CMD_KGDB)
537#define CONFIG_KGDB_BAUDRATE 230400
538#endif
539
540
541
542
543#define CONFIG_HOSTNAME mpc8569mds
544#define CONFIG_ROOTPATH "/nfsroot"
545#define CONFIG_BOOTFILE "your.uImage"
546
547#define CONFIG_SERVERIP 192.168.1.1
548#define CONFIG_GATEWAYIP 192.168.1.1
549#define CONFIG_NETMASK 255.255.255.0
550
551#define CONFIG_LOADADDR 200000
552
553#define CONFIG_BOOTDELAY 10
554#undef CONFIG_BOOTARGS
555
556#define CONFIG_BAUDRATE 115200
557
558#define CONFIG_EXTRA_ENV_SETTINGS \
559 "netdev=eth0\0" \
560 "consoledev=ttyS0\0" \
561 "ramdiskaddr=600000\0" \
562 "ramdiskfile=your.ramdisk.u-boot\0" \
563 "fdtaddr=400000\0" \
564 "fdtfile=your.fdt.dtb\0" \
565 "nfsargs=setenv bootargs root=/dev/nfs rw " \
566 "nfsroot=$serverip:$rootpath " \
567 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
568 "console=$consoledev,$baudrate $othbootargs\0" \
569 "ramargs=setenv bootargs root=/dev/ram rw " \
570 "console=$consoledev,$baudrate $othbootargs\0" \
571
572#define CONFIG_NFSBOOTCOMMAND \
573 "run nfsargs;" \
574 "tftp $loadaddr $bootfile;" \
575 "tftp $fdtaddr $fdtfile;" \
576 "bootm $loadaddr - $fdtaddr"
577
578#define CONFIG_RAMBOOTCOMMAND \
579 "run ramargs;" \
580 "tftp $ramdiskaddr $ramdiskfile;" \
581 "tftp $loadaddr $bootfile;" \
582 "bootm $loadaddr $ramdiskaddr"
583
584#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
585
586#endif
587