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11#ifndef __T1024QDS_H
12#define __T1024QDS_H
13
14
15#define CONFIG_SYS_GENERIC_BOARD
16#define CONFIG_DISPLAY_BOARDINFO
17#define CONFIG_BOOKE
18#define CONFIG_E500
19#define CONFIG_E500MC
20#define CONFIG_SYS_BOOK3E_HV
21#define CONFIG_MP
22#define CONFIG_PHYS_64BIT
23#define CONFIG_ENABLE_36BIT_PHYS
24
25#ifdef CONFIG_PHYS_64BIT
26#define CONFIG_ADDR_MAP 1
27#define CONFIG_SYS_NUM_ADDR_MAP 64
28#endif
29
30#define CONFIG_SYS_FSL_CPC
31#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
32#define CONFIG_FSL_IFC
33
34#define CONFIG_FSL_LAW
35#define CONFIG_ENV_OVERWRITE
36
37#define CONFIG_DEEP_SLEEP
38#if defined(CONFIG_DEEP_SLEEP)
39#define CONFIG_SILENT_CONSOLE
40#define CONFIG_BOARD_EARLY_INIT_F
41#endif
42
43#ifdef CONFIG_RAMBOOT_PBL
44#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
45#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg
46#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
47#define CONFIG_SPL_ENV_SUPPORT
48#define CONFIG_SPL_SERIAL_SUPPORT
49#define CONFIG_SPL_FLUSH_IMAGE
50#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
51#define CONFIG_SPL_LIBGENERIC_SUPPORT
52#define CONFIG_SPL_LIBCOMMON_SUPPORT
53#define CONFIG_SPL_I2C_SUPPORT
54#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
55#define CONFIG_FSL_LAW
56#define CONFIG_SYS_TEXT_BASE 0x00201000
57#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
58#define CONFIG_SPL_PAD_TO 0x40000
59#define CONFIG_SPL_MAX_SIZE 0x28000
60#define RESET_VECTOR_OFFSET 0x27FFC
61#define BOOT_PAGE_OFFSET 0x27000
62#ifdef CONFIG_SPL_BUILD
63#define CONFIG_SPL_SKIP_RELOCATE
64#define CONFIG_SPL_COMMON_INIT_DDR
65#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
66#define CONFIG_SYS_NO_FLASH
67#endif
68
69#ifdef CONFIG_NAND
70#define CONFIG_SPL_NAND_SUPPORT
71#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
72#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
73#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
74#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
75#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
76#define CONFIG_SPL_NAND_BOOT
77#endif
78
79#ifdef CONFIG_SPIFLASH
80#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
81#define CONFIG_SPL_SPI_SUPPORT
82#define CONFIG_SPL_SPI_FLASH_SUPPORT
83#define CONFIG_SPL_SPI_FLASH_MINIMAL
84#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
85#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
86#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
87#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
88#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
89#ifndef CONFIG_SPL_BUILD
90#define CONFIG_SYS_MPC85XX_NO_RESETVEC
91#endif
92#define CONFIG_SPL_SPI_BOOT
93#endif
94
95#ifdef CONFIG_SDCARD
96#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
97#define CONFIG_SPL_MMC_SUPPORT
98#define CONFIG_SPL_MMC_MINIMAL
99#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
100#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
101#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
102#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
103#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
104#ifndef CONFIG_SPL_BUILD
105#define CONFIG_SYS_MPC85XX_NO_RESETVEC
106#endif
107#define CONFIG_SPL_MMC_BOOT
108#endif
109
110#endif
111
112#ifndef CONFIG_SYS_TEXT_BASE
113#define CONFIG_SYS_TEXT_BASE 0xeff40000
114#endif
115
116#ifndef CONFIG_RESET_VECTOR_ADDRESS
117#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
118#endif
119
120#ifndef CONFIG_SYS_NO_FLASH
121#define CONFIG_FLASH_CFI_DRIVER
122#define CONFIG_SYS_FLASH_CFI
123#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
124#endif
125
126
127#define CONFIG_SRIO_PCIE_BOOT_MASTER
128
129
130
131
132#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
133#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
134#ifdef CONFIG_PHYS_64BIT
135#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
136#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
137#else
138#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
139#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
140#endif
141
142
143
144
145#ifdef CONFIG_PHYS_64BIT
146#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
147#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
148#else
149#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
150#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
151#endif
152#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
153
154#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
155#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
156
157
158#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
159#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
160#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
161 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
162
163#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
164#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
165 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
166#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
167#define CONFIG_SYS_NO_FLASH
168#endif
169
170#if defined(CONFIG_SPIFLASH)
171#define CONFIG_SYS_EXTRA_ENV_RELOC
172#define CONFIG_ENV_IS_IN_SPI_FLASH
173#define CONFIG_ENV_SPI_BUS 0
174#define CONFIG_ENV_SPI_CS 0
175#define CONFIG_ENV_SPI_MAX_HZ 10000000
176#define CONFIG_ENV_SPI_MODE 0
177#define CONFIG_ENV_SIZE 0x2000
178#define CONFIG_ENV_OFFSET 0x100000
179#define CONFIG_ENV_SECT_SIZE 0x10000
180#elif defined(CONFIG_SDCARD)
181#define CONFIG_SYS_EXTRA_ENV_RELOC
182#define CONFIG_ENV_IS_IN_MMC
183#define CONFIG_SYS_MMC_ENV_DEV 0
184#define CONFIG_ENV_SIZE 0x2000
185#define CONFIG_ENV_OFFSET (512 * 0x800)
186#elif defined(CONFIG_NAND)
187#define CONFIG_SYS_EXTRA_ENV_RELOC
188#define CONFIG_ENV_IS_IN_NAND
189#define CONFIG_ENV_SIZE 0x2000
190#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
191#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
192#define CONFIG_ENV_IS_IN_REMOTE
193#define CONFIG_ENV_ADDR 0xffe20000
194#define CONFIG_ENV_SIZE 0x2000
195#elif defined(CONFIG_ENV_IS_NOWHERE)
196#define CONFIG_ENV_SIZE 0x2000
197#else
198#define CONFIG_ENV_IS_IN_FLASH
199#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
200#define CONFIG_ENV_SIZE 0x2000
201#define CONFIG_ENV_SECT_SIZE 0x20000
202#endif
203
204
205#ifndef __ASSEMBLY__
206unsigned long get_board_sys_clk(void);
207unsigned long get_board_ddr_clk(void);
208#endif
209
210#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
211#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
212
213
214
215
216#define CONFIG_SYS_CACHE_STASHING
217#define CONFIG_BACKSIDE_L2_CACHE
218#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
219#define CONFIG_BTB
220#define CONFIG_DDR_ECC
221#ifdef CONFIG_DDR_ECC
222#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
223#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
224#endif
225
226#define CONFIG_SYS_MEMTEST_START 0x00200000
227#define CONFIG_SYS_MEMTEST_END 0x00400000
228#define CONFIG_SYS_ALT_MEMTEST
229#define CONFIG_PANIC_HANG
230
231
232
233
234#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
235#define CONFIG_SYS_L3_SIZE (256 << 10)
236#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
237#ifdef CONFIG_RAMBOOT_PBL
238#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
239#endif
240#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
241#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
242#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
243#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
244
245#ifdef CONFIG_PHYS_64BIT
246#define CONFIG_SYS_DCSRBAR 0xf0000000
247#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
248#endif
249
250
251#define CONFIG_ID_EEPROM
252#define CONFIG_SYS_I2C_EEPROM_NXID
253#define CONFIG_SYS_EEPROM_BUS_NUM 0
254#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
255#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
256#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
257#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
258
259
260
261
262#define CONFIG_VERY_BIG_RAM
263#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
264#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
265#define CONFIG_DIMM_SLOTS_PER_CTLR 1
266#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
267#define CONFIG_DDR_SPD
268#ifndef CONFIG_SYS_FSL_DDR4
269#define CONFIG_SYS_FSL_DDR3
270#endif
271
272#define CONFIG_SYS_SPD_BUS_NUM 0
273#define SPD_EEPROM_ADDRESS 0x51
274
275#define CONFIG_SYS_SDRAM_SIZE 4096
276
277
278
279
280#define CONFIG_SYS_FLASH_BASE 0xe0000000
281#ifdef CONFIG_PHYS_64BIT
282#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
283#else
284#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
285#endif
286
287#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
288#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
289 + 0x8000000) | \
290 CSPR_PORT_SIZE_16 | \
291 CSPR_MSEL_NOR | \
292 CSPR_V)
293#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
294#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
295 CSPR_PORT_SIZE_16 | \
296 CSPR_MSEL_NOR | \
297 CSPR_V)
298#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
299
300#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
301#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
302 FTIM0_NOR_TEADC(0x5) | \
303 FTIM0_NOR_TEAHC(0x5))
304#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
305 FTIM1_NOR_TRAD_NOR(0x1A) |\
306 FTIM1_NOR_TSEQRAD_NOR(0x13))
307#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
308 FTIM2_NOR_TCH(0x4) | \
309 FTIM2_NOR_TWPH(0x0E) | \
310 FTIM2_NOR_TWP(0x1c))
311#define CONFIG_SYS_NOR_FTIM3 0x0
312
313#define CONFIG_SYS_FLASH_QUIET_TEST
314#define CONFIG_FLASH_SHOW_PROGRESS 45
315
316#define CONFIG_SYS_MAX_FLASH_BANKS 2
317#define CONFIG_SYS_MAX_FLASH_SECT 1024
318#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
319#define CONFIG_SYS_FLASH_WRITE_TOUT 500
320
321#define CONFIG_SYS_FLASH_EMPTY_INFO
322#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
323 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
324#define CONFIG_FSL_QIXIS
325#define QIXIS_BASE 0xffdf0000
326#ifdef CONFIG_PHYS_64BIT
327#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
328#else
329#define QIXIS_BASE_PHYS QIXIS_BASE
330#endif
331#define QIXIS_LBMAP_SWITCH 0x06
332#define QIXIS_LBMAP_MASK 0x0f
333#define QIXIS_LBMAP_SHIFT 0
334#define QIXIS_LBMAP_DFLTBANK 0x00
335#define QIXIS_LBMAP_ALTBANK 0x04
336#define QIXIS_RST_CTL_RESET 0x31
337#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
338#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
339#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
340#define QIXIS_RST_FORCE_MEM 0x01
341
342#define CONFIG_SYS_CSPR3_EXT (0xf)
343#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
344 | CSPR_PORT_SIZE_8 \
345 | CSPR_MSEL_GPCM \
346 | CSPR_V)
347#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
348#define CONFIG_SYS_CSOR3 0x0
349
350#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
351 FTIM0_GPCM_TEADC(0x0e) | \
352 FTIM0_GPCM_TEAHC(0x0e))
353#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
354 FTIM1_GPCM_TRAD(0x3f))
355#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
356 FTIM2_GPCM_TCH(0x8) | \
357 FTIM2_GPCM_TWP(0x1f))
358#define CONFIG_SYS_CS3_FTIM3 0x0
359
360#define CONFIG_NAND_FSL_IFC
361#define CONFIG_SYS_NAND_BASE 0xff800000
362#ifdef CONFIG_PHYS_64BIT
363#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
364#else
365#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
366#endif
367#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
368#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
369 | CSPR_PORT_SIZE_8 \
370 | CSPR_MSEL_NAND \
371 | CSPR_V)
372#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
373
374#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
375 | CSOR_NAND_ECC_DEC_EN \
376 | CSOR_NAND_ECC_MODE_4 \
377 | CSOR_NAND_RAL_3 \
378 | CSOR_NAND_PGS_2K \
379 | CSOR_NAND_SPRZ_64 \
380 | CSOR_NAND_PB(64))
381
382#define CONFIG_SYS_NAND_ONFI_DETECTION
383
384
385#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
386 FTIM0_NAND_TWP(0x18) | \
387 FTIM0_NAND_TWCHT(0x07) | \
388 FTIM0_NAND_TWH(0x0a))
389#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
390 FTIM1_NAND_TWBE(0x39) | \
391 FTIM1_NAND_TRR(0x0e) | \
392 FTIM1_NAND_TRP(0x18))
393#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
394 FTIM2_NAND_TREH(0x0a) | \
395 FTIM2_NAND_TWHRE(0x1e))
396#define CONFIG_SYS_NAND_FTIM3 0x0
397
398#define CONFIG_SYS_NAND_DDR_LAW 11
399#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
400#define CONFIG_SYS_MAX_NAND_DEVICE 1
401#define CONFIG_CMD_NAND
402
403#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
404
405#if defined(CONFIG_NAND)
406#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
407#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
408#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
409#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
410#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
411#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
412#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
413#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
414#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
415#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
416#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
417#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
418#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
419#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
420#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
421#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
422#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
423#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
424#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
425#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
426#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
427#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
428#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
429#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
430#else
431#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
432#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
433#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
434#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
435#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
436#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
437#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
438#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
439#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
440#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
441#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
442#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
443#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
444#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
445#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
446#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
447#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
448#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
449#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
450#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
451#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
452#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
453#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
454#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
455#endif
456
457#ifdef CONFIG_SPL_BUILD
458#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
459#else
460#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
461#endif
462
463#if defined(CONFIG_RAMBOOT_PBL)
464#define CONFIG_SYS_RAMBOOT
465#endif
466
467#define CONFIG_BOARD_EARLY_INIT_R
468#define CONFIG_MISC_INIT_R
469
470#define CONFIG_HWCONFIG
471
472
473#define CONFIG_L1_INIT_RAM
474#define CONFIG_SYS_INIT_RAM_LOCK
475#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
476#ifdef CONFIG_PHYS_64BIT
477#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
478#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
479
480#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
481 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
482 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
483#else
484#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000
485#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
486#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
487#endif
488#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
489
490#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
491 GENERATED_GBL_DATA_SIZE)
492#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
493
494#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
495#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
496
497
498#define CONFIG_CONS_INDEX 1
499#define CONFIG_SYS_NS16550
500#define CONFIG_SYS_NS16550_SERIAL
501#define CONFIG_SYS_NS16550_REG_SIZE 1
502#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
503
504#define CONFIG_SYS_BAUDRATE_TABLE \
505 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
506
507#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
508#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
509#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
510#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
511#define CONFIG_SYS_CONSOLE_IS_IN_ENV
512
513
514#define CONFIG_SYS_HUSH_PARSER
515#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
516
517
518#ifdef CONFIG_PPC_T1024
519#define CONFIG_FSL_DIU_FB
520#ifdef CONFIG_FSL_DIU_FB
521#define CONFIG_FSL_DIU_CH7301
522#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
523#define CONFIG_VIDEO
524#define CONFIG_CMD_BMP
525#define CONFIG_CFB_CONSOLE
526#define CONFIG_VIDEO_SW_CURSOR
527#define CONFIG_VGA_AS_SINGLE_DEVICE
528#define CONFIG_VIDEO_LOGO
529#define CONFIG_VIDEO_BMP_LOGO
530#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
531
532
533
534
535#undef CONFIG_SYS_FLASH_EMPTY_INFO
536#endif
537#endif
538
539
540#define CONFIG_OF_LIBFDT
541#define CONFIG_OF_BOARD_SETUP
542#define CONFIG_OF_STDOUT_VIA_ALIAS
543
544
545#define CONFIG_FIT
546#define CONFIG_FIT_VERBOSE
547
548
549#define CONFIG_SYS_I2C
550#define CONFIG_SYS_I2C_FSL
551#define CONFIG_SYS_FSL_I2C_SPEED 50000
552#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
553#define CONFIG_SYS_FSL_I2C2_SPEED 50000
554#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
555#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
556#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
557
558#define I2C_MUX_PCA_ADDR 0x77
559#define I2C_MUX_PCA_ADDR_PRI 0x77
560#define I2C_MUX_PCA_ADDR_SEC 0x76
561#define I2C_RETIMER_ADDR 0x18
562
563
564#define I2C_MUX_CH_DEFAULT 0x8
565#define I2C_MUX_CH_DIU 0xC
566#define I2C_MUX_CH5 0xD
567#define I2C_MUX_CH7 0xF
568
569
570#define CONFIG_SYS_I2C_LDI_ADDR 0x38
571#define CONFIG_SYS_I2C_DVI_ADDR 0x75
572
573
574
575
576#define RTC
577#define CONFIG_RTC_DS3231 1
578#define CONFIG_SYS_I2C_RTC_ADDR 0x68
579
580
581
582
583#define CONFIG_FSL_ESPI
584#define CONFIG_SPI_FLASH
585#define CONFIG_SPI_FLASH_STMICRO
586#ifndef CONFIG_SPL_BUILD
587#define CONFIG_SPI_FLASH_SST
588#define CONFIG_SPI_FLASH_EON
589#endif
590#define CONFIG_CMD_SF
591#define CONFIG_SPI_FLASH_BAR
592#define CONFIG_SF_DEFAULT_SPEED 10000000
593#define CONFIG_SF_DEFAULT_MODE 0
594
595
596
597
598
599#define CONFIG_PCI
600#define CONFIG_PCIE1
601#define CONFIG_PCIE2
602#define CONFIG_PCIE3
603#define CONFIG_FSL_PCI_INIT
604#define CONFIG_SYS_PCI_64BIT
605#define CONFIG_PCI_INDIRECT_BRIDGE
606
607#ifdef CONFIG_PCI
608
609#ifdef CONFIG_PCIE1
610#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
611#ifdef CONFIG_PHYS_64BIT
612#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
613#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
614#else
615#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
616#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
617#endif
618#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
619#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
620#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
621#ifdef CONFIG_PHYS_64BIT
622#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
623#else
624#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
625#endif
626#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
627#endif
628
629
630#ifdef CONFIG_PCIE2
631#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
632#ifdef CONFIG_PHYS_64BIT
633#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
634#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
635#else
636#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
637#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
638#endif
639#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
640#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
641#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
642#ifdef CONFIG_PHYS_64BIT
643#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
644#else
645#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
646#endif
647#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
648#endif
649
650
651#ifdef CONFIG_PCIE3
652#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
653#ifdef CONFIG_PHYS_64BIT
654#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
655#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
656#else
657#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
658#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
659#endif
660#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
661#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
662#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
663#ifdef CONFIG_PHYS_64BIT
664#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
665#else
666#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
667#endif
668#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
669#endif
670
671#define CONFIG_PCI_PNP
672#define CONFIG_E1000
673#define CONFIG_PCI_SCAN_SHOW
674#define CONFIG_DOS_PARTITION
675#endif
676
677
678
679
680#define CONFIG_FSL_SATA_V2
681#ifdef CONFIG_FSL_SATA_V2
682#define CONFIG_LIBATA
683#define CONFIG_FSL_SATA
684#define CONFIG_SYS_SATA_MAX_DEVICE 1
685#define CONFIG_SATA1
686#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
687#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
688#define CONFIG_LBA48
689#define CONFIG_CMD_SATA
690#define CONFIG_DOS_PARTITION
691#define CONFIG_CMD_EXT2
692#endif
693
694
695
696
697#define CONFIG_HAS_FSL_DR_USB
698
699#ifdef CONFIG_HAS_FSL_DR_USB
700#define CONFIG_USB_EHCI
701#define CONFIG_CMD_USB
702#define CONFIG_USB_STORAGE
703#define CONFIG_USB_EHCI_FSL
704#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
705#define CONFIG_CMD_EXT2
706#endif
707
708
709
710
711#define CONFIG_MMC
712#ifdef CONFIG_MMC
713#define CONFIG_FSL_ESDHC
714#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
715#define CONFIG_CMD_MMC
716#define CONFIG_GENERIC_MMC
717#define CONFIG_CMD_EXT2
718#define CONFIG_CMD_FAT
719#define CONFIG_DOS_PARTITION
720#endif
721
722
723#ifndef CONFIG_NOBQFMAN
724#define CONFIG_SYS_DPAA_QBMAN
725#define CONFIG_SYS_BMAN_NUM_PORTALS 10
726#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
727#ifdef CONFIG_PHYS_64BIT
728#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
729#else
730#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
731#endif
732#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
733#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
734#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
735#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
736#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
737#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
738 CONFIG_SYS_BMAN_CENA_SIZE)
739#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
740#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
741#define CONFIG_SYS_QMAN_NUM_PORTALS 10
742#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
743#ifdef CONFIG_PHYS_64BIT
744#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
745#else
746#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
747#endif
748#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
749#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
750#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
751#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
752#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
753#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
754 CONFIG_SYS_QMAN_CENA_SIZE)
755#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
756#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
757
758#define CONFIG_SYS_DPAA_FMAN
759
760#define CONFIG_QE
761#define CONFIG_U_QE
762
763#if defined(CONFIG_SPIFLASH)
764
765
766
767
768#define CONFIG_SYS_QE_FW_IN_SPIFLASH
769#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
770#define CONFIG_SYS_QE_FW_ADDR 0x130000
771#elif defined(CONFIG_SDCARD)
772
773
774
775
776
777#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
778#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
779#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
780#elif defined(CONFIG_NAND)
781#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
782#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
783#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
784#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
785
786
787
788
789
790
791
792#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
793#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
794#else
795#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
796#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
797#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
798#endif
799#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
800#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
801#endif
802
803#ifdef CONFIG_SYS_DPAA_FMAN
804#define CONFIG_FMAN_ENET
805#define CONFIG_PHYLIB_10G
806#define CONFIG_PHY_VITESSE
807#define CONFIG_PHY_REALTEK
808#define CONFIG_PHY_TERANETICS
809#define RGMII_PHY1_ADDR 0x1
810#define RGMII_PHY2_ADDR 0x2
811#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
812#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
813#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
814#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
815#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
816#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
817#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
818#endif
819
820#ifdef CONFIG_FMAN_ENET
821#define CONFIG_MII
822#define CONFIG_ETHPRIME "FM1@DTSEC4"
823#define CONFIG_PHY_GIGE
824#endif
825
826
827
828
829#ifndef CONFIG_SYS_NO_FLASH
830#define CONFIG_MTD_DEVICE
831#define CONFIG_MTD_PARTITIONS
832#define CONFIG_CMD_MTDPARTS
833#define CONFIG_FLASH_CFI_MTD
834#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
835 "spi0=spife110000.0"
836#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
837 "128k(dtb),96m(fs),-(user);"\
838 "fff800000.flash:2m(uboot),9m(kernel),"\
839 "128k(dtb),96m(fs),-(user);spife110000.0:" \
840 "2m(uboot),9m(kernel),128k(dtb),-(user)"
841#endif
842
843
844
845
846#define CONFIG_LOADS_ECHO
847#define CONFIG_SYS_LOADS_BAUD_CHANGE
848
849
850
851
852#include <config_cmd_default.h>
853
854#define CONFIG_CMD_DATE
855#define CONFIG_CMD_DHCP
856#define CONFIG_CMD_EEPROM
857#define CONFIG_CMD_ELF
858#define CONFIG_CMD_ERRATA
859#define CONFIG_CMD_GREPENV
860#define CONFIG_CMD_IRQ
861#define CONFIG_CMD_I2C
862#define CONFIG_CMD_MII
863#define CONFIG_CMD_PING
864#define CONFIG_CMD_REGINFO
865#define CONFIG_CMD_SETEXPR
866
867#ifdef CONFIG_PCI
868#define CONFIG_CMD_PCI
869#define CONFIG_CMD_NET
870#endif
871
872
873
874
875#define CONFIG_SYS_LONGHELP
876#define CONFIG_CMDLINE_EDITING
877#define CONFIG_AUTO_COMPLETE
878#define CONFIG_SYS_LOAD_ADDR 0x2000000
879#define CONFIG_SYS_PROMPT "=> "
880#ifdef CONFIG_CMD_KGDB
881#define CONFIG_SYS_CBSIZE 1024
882#else
883#define CONFIG_SYS_CBSIZE 256
884#endif
885#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
886#define CONFIG_SYS_MAXARGS 16
887#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
888
889
890
891
892
893
894#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
895#define CONFIG_SYS_BOOTM_LEN (64 << 20)
896
897#ifdef CONFIG_CMD_KGDB
898#define CONFIG_KGDB_BAUDRATE 230400
899#endif
900
901
902
903
904#define CONFIG_ROOTPATH "/opt/nfsroot"
905#define CONFIG_BOOTFILE "uImage"
906#define CONFIG_UBOOTPATH "u-boot.bin"
907#define CONFIG_LOADADDR 1000000
908#define CONFIG_BOOTDELAY 10
909#define CONFIG_BAUDRATE 115200
910#define __USB_PHY_TYPE utmi
911
912
913#define CONFIG_EXTRA_ENV_SETTINGS \
914 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
915 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
916 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
917 "ramdiskfile=t1024qds/ramdisk.uboot\0" \
918 "fdtfile=t1024qds/t1024qds.dtb\0" \
919 "netdev=eth0\0" \
920 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
921 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
922 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
923 "tftpflash=tftpboot $loadaddr $uboot && " \
924 "protect off $ubootaddr +$filesize && " \
925 "erase $ubootaddr +$filesize && " \
926 "cp.b $loadaddr $ubootaddr $filesize && " \
927 "protect on $ubootaddr +$filesize && " \
928 "cmp.b $loadaddr $ubootaddr $filesize\0" \
929 "consoledev=ttyS0\0" \
930 "ramdiskaddr=2000000\0" \
931 "fdtaddr=d00000\0" \
932 "bdev=sda3\0"
933
934#define CONFIG_LINUX \
935 "setenv bootargs root=/dev/ram rw " \
936 "console=$consoledev,$baudrate $othbootargs;" \
937 "setenv ramdiskaddr 0x02000000;" \
938 "setenv fdtaddr 0x00c00000;" \
939 "setenv loadaddr 0x1000000;" \
940 "bootm $loadaddr $ramdiskaddr $fdtaddr"
941
942#define CONFIG_NFSBOOTCOMMAND \
943 "setenv bootargs root=/dev/nfs rw " \
944 "nfsroot=$serverip:$rootpath " \
945 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
946 "console=$consoledev,$baudrate $othbootargs;" \
947 "tftp $loadaddr $bootfile;" \
948 "tftp $fdtaddr $fdtfile;" \
949 "bootm $loadaddr - $fdtaddr"
950
951#define CONFIG_BOOTCOMMAND CONFIG_LINUX
952
953#ifdef CONFIG_SECURE_BOOT
954#include <asm/fsl_secure_boot.h>
955#endif
956
957#endif
958