1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ 21#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ 22#define CONFIG_SYS_GENERIC_BOARD 23#define CONFIG_DISPLAY_BOARDINFO 24 25#define CONFIG_SYS_TEXT_BASE 0x40000000 26 27#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 28#define CONFIG_SYS_SMC_RXBUFLEN 128 29#define CONFIG_SYS_MAXIDLE 10 30#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 31 32#define CONFIG_BOOTCOUNT_LIMIT 33 34#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 35 36#define CONFIG_BOARD_TYPES 1 /* support board types */ 37 38#define CONFIG_PREBOOT "echo;" \ 39 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 40 "echo" 41 42#undef CONFIG_BOOTARGS 43 44#define CONFIG_EXTRA_ENV_SETTINGS \ 45 "netdev=eth0\0" \ 46 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 47 "nfsroot=${serverip}:${rootpath}\0" \ 48 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 49 "addip=setenv bootargs ${bootargs} " \ 50 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 51 ":${hostname}:${netdev}:off panic=1\0" \ 52 "flash_nfs=run nfsargs addip;" \ 53 "bootm ${kernel_addr}\0" \ 54 "flash_self=run ramargs addip;" \ 55 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 56 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 57 "rootpath=/opt/eldk/ppc_8xx\0" \ 58 "hostname=TQM860M\0" \ 59 "bootfile=TQM860M/uImage\0" \ 60 "fdt_addr=400C0000\0" \ 61 "kernel_addr=40100000\0" \ 62 "ramdisk_addr=40280000\0" \ 63 "u-boot=TQM860M/u-image.bin\0" \ 64 "load=tftp 200000 ${u-boot}\0" \ 65 "update=prot off 40000000 +${filesize};" \ 66 "era 40000000 +${filesize};" \ 67 "cp.b 200000 40000000 ${filesize};" \ 68 "sete filesize;save\0" \ 69 "" 70#define CONFIG_BOOTCOMMAND "run flash_self" 71 72#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 73#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 74 75#undef CONFIG_WATCHDOG /* watchdog disabled */ 76 77#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 78 79#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 80 81/* 82 * BOOTP options 83 */ 84#define CONFIG_BOOTP_SUBNETMASK 85#define CONFIG_BOOTP_GATEWAY 86#define CONFIG_BOOTP_HOSTNAME 87#define CONFIG_BOOTP_BOOTPATH 88#define CONFIG_BOOTP_BOOTFILESIZE 89 90 91#define CONFIG_MAC_PARTITION 92#define CONFIG_DOS_PARTITION 93 94#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 95 96 97/* 98 * Command line configuration. 99 */ 100#include <config_cmd_default.h> 101 102#define CONFIG_CMD_ASKENV 103#define CONFIG_CMD_DATE 104#define CONFIG_CMD_DHCP 105#define CONFIG_CMD_ELF 106#define CONFIG_CMD_EXT2 107#define CONFIG_CMD_IDE 108#define CONFIG_CMD_JFFS2 109#define CONFIG_CMD_NFS 110#define CONFIG_CMD_SNTP 111 112 113#define CONFIG_NETCONSOLE 114 115 116/* 117 * Miscellaneous configurable options 118 */ 119#define CONFIG_SYS_LONGHELP /* undef to save memory */ 120 121#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 122#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 123 124#if defined(CONFIG_CMD_KGDB) 125#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 126#else 127#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 128#endif 129#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 130#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 131#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 132 133#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 134#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 135 136#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 137 138/* 139 * Low Level Configuration Settings 140 * (address mappings, register initial values, etc.) 141 * You should know what you are doing if you make changes here. 142 */ 143/*----------------------------------------------------------------------- 144 * Internal Memory Mapped Register 145 */ 146#define CONFIG_SYS_IMMR 0xFFF00000 147 148/*----------------------------------------------------------------------- 149 * Definitions for initial stack pointer and data area (in DPRAM) 150 */ 151#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 152#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 153#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 154#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 155 156/*----------------------------------------------------------------------- 157 * Start addresses for the final memory configuration 158 * (Set up by the startup code) 159 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 160 */ 161#define CONFIG_SYS_SDRAM_BASE 0x00000000 162#define CONFIG_SYS_FLASH_BASE 0x40000000 163#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 164#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 165#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ 166 167/* 168 * For booting Linux, the board info and command line data 169 * have to be in the first 8 MB of memory, since this is 170 * the maximum mapped by the Linux kernel during initialization. 171 */ 172#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 173 174/*----------------------------------------------------------------------- 175 * FLASH organization 176 */ 177/* use CFI flash driver */ 178#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 179#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 180#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 181#define CONFIG_SYS_FLASH_EMPTY_INFO 182#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 183#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 184#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 185 186#define CONFIG_ENV_IS_IN_FLASH 1 187#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 188#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ 189#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ 190 191/* Address and size of Redundant Environment Sector */ 192#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 193#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 194 195#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 196 197#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 198 199/*----------------------------------------------------------------------- 200 * Dynamic MTD partition support 201 */ 202#define CONFIG_CMD_MTDPARTS 203#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 204#define CONFIG_FLASH_CFI_MTD 205#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 206 207#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 208 "128k(dtb)," \ 209 "1920k(kernel)," \ 210 "5632(rootfs)," \ 211 "4m(data)" 212 213/*----------------------------------------------------------------------- 214 * Hardware Information Block 215 */ 216#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 217#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 218#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 219 220/*----------------------------------------------------------------------- 221 * Cache Configuration 222 */ 223#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 224#if defined(CONFIG_CMD_KGDB) 225#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 226#endif 227 228/*----------------------------------------------------------------------- 229 * SYPCR - System Protection Control 11-9 230 * SYPCR can only be written once after reset! 231 *----------------------------------------------------------------------- 232 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 233 */ 234#if defined(CONFIG_WATCHDOG) 235#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 236 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 237#else 238#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 239#endif 240 241/*----------------------------------------------------------------------- 242 * SIUMCR - SIU Module Configuration 11-6 243 *----------------------------------------------------------------------- 244 * PCMCIA config., multi-function pin tri-state 245 */ 246#ifndef CONFIG_CAN_DRIVER 247#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 248#else /* we must activate GPL5 in the SIUMCR for CAN */ 249#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 250#endif /* CONFIG_CAN_DRIVER */ 251 252/*----------------------------------------------------------------------- 253 * TBSCR - Time Base Status and Control 11-26 254 *----------------------------------------------------------------------- 255 * Clear Reference Interrupt Status, Timebase freezing enabled 256 */ 257#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 258 259/*----------------------------------------------------------------------- 260 * RTCSC - Real-Time Clock Status and Control Register 11-27 261 *----------------------------------------------------------------------- 262 */ 263#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 264 265/*----------------------------------------------------------------------- 266 * PISCR - Periodic Interrupt Status and Control 11-31 267 *----------------------------------------------------------------------- 268 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 269 */ 270#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 271 272/*----------------------------------------------------------------------- 273 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 274 *----------------------------------------------------------------------- 275 * Reset PLL lock status sticky bit, timer expired status bit and timer 276 * interrupt status bit 277 */ 278#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 279 280/*----------------------------------------------------------------------- 281 * SCCR - System Clock and reset Control Register 15-27 282 *----------------------------------------------------------------------- 283 * Set clock output, timebase and RTC source and divider, 284 * power management and some other internal clocks 285 */ 286#define SCCR_MASK SCCR_EBDF11 287#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 288 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 289 SCCR_DFALCD00) 290 291/*----------------------------------------------------------------------- 292 * PCMCIA stuff 293 *----------------------------------------------------------------------- 294 * 295 */ 296#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 297#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 298#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 299#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 300#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 301#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 302#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 303#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 304 305/*----------------------------------------------------------------------- 306 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 307 *----------------------------------------------------------------------- 308 */ 309 310#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 311#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 312 313#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 314#undef CONFIG_IDE_LED /* LED for ide not supported */ 315#undef CONFIG_IDE_RESET /* reset for ide not supported */ 316 317#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 318#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 319 320#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 321 322#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 323 324/* Offset for data I/O */ 325#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 326 327/* Offset for normal register accesses */ 328#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 329 330/* Offset for alternate registers */ 331#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 332 333/*----------------------------------------------------------------------- 334 * 335 *----------------------------------------------------------------------- 336 * 337 */ 338#define CONFIG_SYS_DER 0 339 340/* 341 * Init Memory Controller: 342 * 343 * BR0/1 and OR0/1 (FLASH) 344 */ 345 346#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 347#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 348 349/* used to re-map FLASH both when starting from SRAM or FLASH: 350 * restrict access enough to keep SRAM working (if any) 351 * but not too much to meddle with FLASH accesses 352 */ 353#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 354#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 355 356/* 357 * FLASH timing: 358 */ 359#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 360 OR_SCY_3_CLK | OR_EHTR | OR_BI) 361 362#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 363#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 364#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 365 366#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 367#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 368#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 369 370/* 371 * BR2/3 and OR2/3 (SDRAM) 372 * 373 */ 374#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 375#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 376#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */ 377 378/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 379#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 380 381#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 382#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 383 384#ifndef CONFIG_CAN_DRIVER 385#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 386#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 387#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 388#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 389#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 390#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 391#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 392 BR_PS_8 | BR_MS_UPMB | BR_V ) 393#endif /* CONFIG_CAN_DRIVER */ 394 395/* 396 * Memory Periodic Timer Prescaler 397 * 398 * The Divider for PTA (refresh timer) configuration is based on an 399 * example SDRAM configuration (64 MBit, one bank). The adjustment to 400 * the number of chip selects (NCS) and the actually needed refresh 401 * rate is done by setting MPTPR. 402 * 403 * PTA is calculated from 404 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 405 * 406 * gclk CPU clock (not bus clock!) 407 * Trefresh Refresh cycle * 4 (four word bursts used) 408 * 409 * 4096 Rows from SDRAM example configuration 410 * 1000 factor s -> ms 411 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 412 * 4 Number of refresh cycles per period 413 * 64 Refresh cycle in ms per number of rows 414 * -------------------------------------------- 415 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 416 * 417 * 50 MHz => 50.000.000 / Divider = 98 418 * 66 Mhz => 66.000.000 / Divider = 129 419 * 80 Mhz => 80.000.000 / Divider = 156 420 */ 421 422#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 423#define CONFIG_SYS_MAMR_PTA 98 424 425/* 426 * For 16 MBit, refresh rates could be 31.3 us 427 * (= 64 ms / 2K = 125 / quad bursts). 428 * For a simpler initialization, 15.6 us is used instead. 429 * 430 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 431 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 432 */ 433#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 434#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 435 436/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 437#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 438#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 439 440/* 441 * MAMR settings for SDRAM 442 */ 443 444/* 8 column SDRAM */ 445#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 446 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 447 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 448/* 9 column SDRAM */ 449#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 450 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 451 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 452/* 10 column SDRAM */ 453#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 454 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ 455 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 456 457#define CONFIG_SCC1_ENET 458#define CONFIG_FEC_ENET 459#define CONFIG_ETHPRIME "SCC" 460 461/* pass open firmware flat tree */ 462#define CONFIG_OF_LIBFDT 1 463#define CONFIG_OF_BOARD_SETUP 1 464#define CONFIG_HWCONFIG 1 465 466#endif /* __CONFIG_H */ 467