1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC860 1 21#define CONFIG_MPC860T 1 22#define CONFIG_MPC862 1 23#define CONFIG_SYS_GENERIC_BOARD 24#define CONFIG_DISPLAY_BOARDINFO 25 26#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ 27 28#define CONFIG_SYS_TEXT_BASE 0x40000000 29 30#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 31#define CONFIG_SYS_SMC_RXBUFLEN 128 32#define CONFIG_SYS_MAXIDLE 10 33#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 34 35#define CONFIG_BOOTCOUNT_LIMIT 36 37#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 38 39#define CONFIG_BOARD_TYPES 1 /* support board types */ 40 41#define CONFIG_PREBOOT "echo;" \ 42 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 43 "echo" 44 45#undef CONFIG_BOOTARGS 46 47#define CONFIG_EXTRA_ENV_SETTINGS \ 48 "netdev=eth0\0" \ 49 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 50 "nfsroot=${serverip}:${rootpath}\0" \ 51 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 52 "addip=setenv bootargs ${bootargs} " \ 53 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 54 ":${hostname}:${netdev}:off panic=1\0" \ 55 "flash_nfs=run nfsargs addip;" \ 56 "bootm ${kernel_addr}\0" \ 57 "flash_self=run ramargs addip;" \ 58 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 59 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 60 "rootpath=/opt/eldk/ppc_8xx\0" \ 61 "hostname=TQM862L\0" \ 62 "bootfile=TQM862L/uImage\0" \ 63 "fdt_addr=40040000\0" \ 64 "kernel_addr=40060000\0" \ 65 "ramdisk_addr=40200000\0" \ 66 "u-boot=TQM862L/u-image.bin\0" \ 67 "load=tftp 200000 ${u-boot}\0" \ 68 "update=prot off 40000000 +${filesize};" \ 69 "era 40000000 +${filesize};" \ 70 "cp.b 200000 40000000 ${filesize};" \ 71 "sete filesize;save\0" \ 72 "" 73#define CONFIG_BOOTCOMMAND "run flash_self" 74 75#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 76#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 77 78#undef CONFIG_WATCHDOG /* watchdog disabled */ 79 80#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 81 82#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 83 84/* 85 * BOOTP options 86 */ 87#define CONFIG_BOOTP_SUBNETMASK 88#define CONFIG_BOOTP_GATEWAY 89#define CONFIG_BOOTP_HOSTNAME 90#define CONFIG_BOOTP_BOOTPATH 91#define CONFIG_BOOTP_BOOTFILESIZE 92 93 94#define CONFIG_MAC_PARTITION 95#define CONFIG_DOS_PARTITION 96 97#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 98 99 100/* 101 * Command line configuration. 102 */ 103#include <config_cmd_default.h> 104 105#define CONFIG_CMD_ASKENV 106#define CONFIG_CMD_DATE 107#define CONFIG_CMD_DHCP 108#define CONFIG_CMD_ELF 109#define CONFIG_CMD_EXT2 110#define CONFIG_CMD_IDE 111#define CONFIG_CMD_JFFS2 112#define CONFIG_CMD_NFS 113#define CONFIG_CMD_SNTP 114 115 116#define CONFIG_NETCONSOLE 117 118 119/* 120 * Miscellaneous configurable options 121 */ 122#define CONFIG_SYS_LONGHELP /* undef to save memory */ 123 124#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 125#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 126 127#if defined(CONFIG_CMD_KGDB) 128#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 129#else 130#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 131#endif 132#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 133#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 134#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 135 136#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 137#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 138 139#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 140 141/* 142 * Low Level Configuration Settings 143 * (address mappings, register initial values, etc.) 144 * You should know what you are doing if you make changes here. 145 */ 146/*----------------------------------------------------------------------- 147 * Internal Memory Mapped Register 148 */ 149#define CONFIG_SYS_IMMR 0xFFF00000 150 151/*----------------------------------------------------------------------- 152 * Definitions for initial stack pointer and data area (in DPRAM) 153 */ 154#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 155#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 156#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 157#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 158 159/*----------------------------------------------------------------------- 160 * Start addresses for the final memory configuration 161 * (Set up by the startup code) 162 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 163 */ 164#define CONFIG_SYS_SDRAM_BASE 0x00000000 165#define CONFIG_SYS_FLASH_BASE 0x40000000 166#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 167#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 168#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 169 170/* 171 * For booting Linux, the board info and command line data 172 * have to be in the first 8 MB of memory, since this is 173 * the maximum mapped by the Linux kernel during initialization. 174 */ 175#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 176 177/*----------------------------------------------------------------------- 178 * FLASH organization 179 */ 180 181/* use CFI flash driver */ 182#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 183#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 184#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 185#define CONFIG_SYS_FLASH_EMPTY_INFO 186#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 187#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 188#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 189 190#define CONFIG_ENV_IS_IN_FLASH 1 191#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 192#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 193 194/* Address and size of Redundant Environment Sector */ 195#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 196#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 197 198#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 199 200#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 201 202/*----------------------------------------------------------------------- 203 * Dynamic MTD partition support 204 */ 205#define CONFIG_CMD_MTDPARTS 206#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 207#define CONFIG_FLASH_CFI_MTD 208#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 209 210#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 211 "128k(dtb)," \ 212 "1664k(kernel)," \ 213 "2m(rootfs)," \ 214 "4m(data)" 215 216/*----------------------------------------------------------------------- 217 * Hardware Information Block 218 */ 219#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 220#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 221#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 222 223/*----------------------------------------------------------------------- 224 * Cache Configuration 225 */ 226#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 227#if defined(CONFIG_CMD_KGDB) 228#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 229#endif 230 231/*----------------------------------------------------------------------- 232 * SYPCR - System Protection Control 11-9 233 * SYPCR can only be written once after reset! 234 *----------------------------------------------------------------------- 235 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 236 */ 237#if defined(CONFIG_WATCHDOG) 238#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 239 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 240#else 241#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 242#endif 243 244/*----------------------------------------------------------------------- 245 * SIUMCR - SIU Module Configuration 11-6 246 *----------------------------------------------------------------------- 247 * PCMCIA config., multi-function pin tri-state 248 */ 249#ifndef CONFIG_CAN_DRIVER 250#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 251#else /* we must activate GPL5 in the SIUMCR for CAN */ 252#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 253#endif /* CONFIG_CAN_DRIVER */ 254 255/*----------------------------------------------------------------------- 256 * TBSCR - Time Base Status and Control 11-26 257 *----------------------------------------------------------------------- 258 * Clear Reference Interrupt Status, Timebase freezing enabled 259 */ 260#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 261 262/*----------------------------------------------------------------------- 263 * RTCSC - Real-Time Clock Status and Control Register 11-27 264 *----------------------------------------------------------------------- 265 */ 266#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 267 268/*----------------------------------------------------------------------- 269 * PISCR - Periodic Interrupt Status and Control 11-31 270 *----------------------------------------------------------------------- 271 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 272 */ 273#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 274 275/*----------------------------------------------------------------------- 276 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 277 *----------------------------------------------------------------------- 278 * Reset PLL lock status sticky bit, timer expired status bit and timer 279 * interrupt status bit 280 */ 281#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 282 283/*----------------------------------------------------------------------- 284 * SCCR - System Clock and reset Control Register 15-27 285 *----------------------------------------------------------------------- 286 * Set clock output, timebase and RTC source and divider, 287 * power management and some other internal clocks 288 */ 289#define SCCR_MASK SCCR_EBDF11 290#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 291 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 292 SCCR_DFALCD00) 293 294/*----------------------------------------------------------------------- 295 * PCMCIA stuff 296 *----------------------------------------------------------------------- 297 * 298 */ 299#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 300#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 301#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 302#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 303#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 304#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 305#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 306#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 307 308/*----------------------------------------------------------------------- 309 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 310 *----------------------------------------------------------------------- 311 */ 312 313#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 314#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 315 316#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 317#undef CONFIG_IDE_LED /* LED for ide not supported */ 318#undef CONFIG_IDE_RESET /* reset for ide not supported */ 319 320#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 321#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 322 323#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 324 325#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 326 327/* Offset for data I/O */ 328#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 329 330/* Offset for normal register accesses */ 331#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 332 333/* Offset for alternate registers */ 334#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 335 336/*----------------------------------------------------------------------- 337 * 338 *----------------------------------------------------------------------- 339 * 340 */ 341#define CONFIG_SYS_DER 0 342 343/* 344 * Init Memory Controller: 345 * 346 * BR0/1 and OR0/1 (FLASH) 347 */ 348 349#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 350#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ 351 352/* used to re-map FLASH both when starting from SRAM or FLASH: 353 * restrict access enough to keep SRAM working (if any) 354 * but not too much to meddle with FLASH accesses 355 */ 356#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 357#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 358 359/* 360 * FLASH timing: 361 */ 362#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 363 OR_SCY_3_CLK | OR_EHTR | OR_BI) 364 365#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 366#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 367#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 368 369#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 370#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 371#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 372 373/* 374 * BR2/3 and OR2/3 (SDRAM) 375 * 376 */ 377#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 378#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 379#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 380 381/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 382#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 383 384#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 385#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 386 387#ifndef CONFIG_CAN_DRIVER 388#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 389#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 390#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 391#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 392#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 393#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 394#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 395 BR_PS_8 | BR_MS_UPMB | BR_V ) 396#endif /* CONFIG_CAN_DRIVER */ 397 398/* 399 * Memory Periodic Timer Prescaler 400 * 401 * The Divider for PTA (refresh timer) configuration is based on an 402 * example SDRAM configuration (64 MBit, one bank). The adjustment to 403 * the number of chip selects (NCS) and the actually needed refresh 404 * rate is done by setting MPTPR. 405 * 406 * PTA is calculated from 407 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 408 * 409 * gclk CPU clock (not bus clock!) 410 * Trefresh Refresh cycle * 4 (four word bursts used) 411 * 412 * 4096 Rows from SDRAM example configuration 413 * 1000 factor s -> ms 414 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 415 * 4 Number of refresh cycles per period 416 * 64 Refresh cycle in ms per number of rows 417 * -------------------------------------------- 418 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 419 * 420 * 50 MHz => 50.000.000 / Divider = 98 421 * 66 Mhz => 66.000.000 / Divider = 129 422 * 80 Mhz => 80.000.000 / Divider = 156 423 * 100 Mhz => 100.000.000 / Divider = 195 424 */ 425 426#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 427#define CONFIG_SYS_MAMR_PTA 98 428 429/* 430 * For 16 MBit, refresh rates could be 31.3 us 431 * (= 64 ms / 2K = 125 / quad bursts). 432 * For a simpler initialization, 15.6 us is used instead. 433 * 434 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 435 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 436 */ 437#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 438#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 439 440/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 441#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 442#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 443 444/* 445 * MAMR settings for SDRAM 446 */ 447 448/* 8 column SDRAM */ 449#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 450 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 451 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 452/* 9 column SDRAM */ 453#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 454 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 455 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 456 457#define CONFIG_SCC1_ENET 458#define CONFIG_FEC_ENET 459#define CONFIG_ETHPRIME "SCC" 460 461/* pass open firmware flat tree */ 462#define CONFIG_OF_LIBFDT 1 463#define CONFIG_OF_BOARD_SETUP 1 464#define CONFIG_HWCONFIG 1 465 466#endif /* __CONFIG_H */ 467