1
2
3
4
5
6
7
8
9
10
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_ARIA 1
16#define CONFIG_DISPLAY_BOARDINFO
17#define CONFIG_SYS_GENERIC_BOARD
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36#define CONFIG_E300 1
37#define CONFIG_FSL_DIU_FB 1
38
39#define CONFIG_SYS_TEXT_BASE 0xFFF00000
40
41
42#undef CONFIG_VIDEO
43
44#if defined(CONFIG_VIDEO)
45#define CONFIG_CFB_CONSOLE
46#define CONFIG_VGA_AS_SINGLE_DEVICE
47#endif
48
49
50
51#define CONFIG_SYS_MPC512X_CLKIN 33000000
52
53#define CONFIG_MISC_INIT_R
54
55#define CONFIG_SYS_IMMR 0x80000000
56#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
57
58#define CONFIG_SYS_MEMTEST_START 0x00200000
59#define CONFIG_SYS_MEMTEST_END 0x00400000
60
61
62
63
64#define CONFIG_SYS_DDR_SIZE 256
65#define CONFIG_SYS_DDR_BASE 0x00000000
66#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
67#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
68
69#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | \
116 (1 << 30) | \
117 (1 << 29) | \
118 (0 << 28) | \
119 (4 << 25) | \
120 (3 << 21) | \
121 (0 << 18) | \
122 (0 << 17) | \
123 (2 << 13) | \
124 (0 << 12) | \
125 (1 << 11) | \
126 (2 << 8) | \
127 (0 << 7) | \
128 (1 << 6) | \
129 (0 << 5) | \
130 (0 << 4) | \
131 (0 << 1) | \
132 (0 << 0) \
133 )
134
135#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
136#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
137#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
138
139#define CONFIG_SYS_DDRCMD_NOP 0x01380000
140#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
141#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | \
142 (0 << 22) | \
143 (0 << 21) | \
144 (0 << 20) | \
145 (0 << 19) | \
146 (1 << 16) | \
147 (0 << 15) | \
148 (0 << 12) | \
149 (0 << 11) | \
150 (0 << 10) | \
151 (0 << 7) | \
152 (0 << 6) | \
153 (0 << 3) | \
154 (0 << 2) | \
155 (1 << 1) | \
156 (0 << 0) \
157 )
158#define CONFIG_SYS_MICRON_EMR2 0x01020000
159#define CONFIG_SYS_MICRON_EMR3 0x01030000
160#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
161#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
162#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | \
163 (0 << 22) | \
164 (0 << 21) | \
165 (0 << 20) | \
166 (0 << 19) | \
167 (1 << 16) | \
168 (0 << 15) | \
169 (0 << 12) | \
170 (0 << 11) | \
171 (1 << 10) | \
172 (7 << 7) | \
173 (0 << 6) | \
174 (0 << 3) | \
175 (1 << 2) | \
176 (0 << 1) | \
177 (0 << 0) \
178 )
179
180
181
182
183
184#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
185#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
186#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
187#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
188
189
190#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
191#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
192#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
193#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
194#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
195#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
196#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
197#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
198#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
199#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
200#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
201#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
202#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
203#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
204#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
205#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
206#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
207#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
208#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
209#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
210#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
211#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
212#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
213
214
215
216
217#define CONFIG_SYS_FLASH_CFI
218#define CONFIG_FLASH_CFI_DRIVER
219#define CONFIG_SYS_FLASH_BASE 0xF8000000
220#define CONFIG_SYS_FLASH_SIZE 0x08000000
221
222#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
223#define CONFIG_SYS_MAX_FLASH_BANKS 1
224#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
225#define CONFIG_SYS_MAX_FLASH_SECT 1024
226
227#undef CONFIG_SYS_FLASH_CHECKSUM
228
229
230
231
232
233#define CONFIG_CMD_NAND
234#define CONFIG_JFFS2_NAND
235#define CONFIG_NAND_MPC5121_NFC
236#define CONFIG_SYS_NAND_BASE 0x40000000
237#define CONFIG_SYS_MAX_NAND_DEVICE 1
238
239
240
241
242#define CONFIG_FSL_NFC_WIDTH 1
243#define CONFIG_FSL_NFC_WRITE_SIZE 2048
244#define CONFIG_FSL_NFC_SPARE_SIZE 64
245#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
246
247#define CONFIG_SYS_SRAM_BASE 0x30000000
248#define CONFIG_SYS_SRAM_SIZE 0x00020000
249
250
251#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \
252 CONFIG_SYS_SRAM_SIZE)
253#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000
254#define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE
255#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE
256
257#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \
258 CONFIG_SYS_ARIA_SRAM_SIZE)
259#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000
260
261#define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE
262#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE
263
264#define CONFIG_SYS_CS0_CFG 0x05059150
265#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \
266 (5 << 16) | \
267 (1 << 15) | \
268 (0 << 14) | \
269 (0 << 13) | \
270 (1 << 12) | \
271 (0 << 10) | \
272 (3 << 8) | \
273 (0 << 7) | \
274 (1 << 6) | \
275 (1 << 4) | \
276 (0 << 3) | \
277 (0 << 2) | \
278 (0 << 1) | \
279 (0 << 0) \
280 )
281#define CONFIG_SYS_CS6_CFG 0x05059150
282
283
284#define CONFIG_SYS_CS_ALETIMING 0x00000005
285
286
287#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
288#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
289
290#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
291 GENERATED_GBL_DATA_SIZE)
292#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
293
294#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
295#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
296
297#ifdef CONFIG_FSL_DIU_FB
298#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
299#else
300#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
301#endif
302
303
304#define CONFIG_ARIA_FPGA 1
305
306
307
308
309#define CONFIG_CONS_INDEX 1
310
311
312
313
314#define CONFIG_PSC_CONSOLE 3
315#define CONFIG_SYS_PSC3
316#if CONFIG_PSC_CONSOLE != 3
317#error CONFIG_PSC_CONSOLE must be 3
318#endif
319
320#define CONFIG_BAUDRATE 115200
321#define CONFIG_SYS_BAUDRATE_TABLE \
322 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
323
324#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
325#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
326#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
327#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
328
329#define CONFIG_CMDLINE_EDITING 1
330
331#define CONFIG_SYS_HUSH_PARSER
332#ifdef CONFIG_SYS_HUSH_PARSER
333#endif
334
335
336
337
338#ifdef CONFIG_PCI
339#define CONFIG_PCI_INDIRECT_BRIDGE
340
341#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
342#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
343#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
344#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \
345 CONFIG_SYS_PCI_MEM_SIZE)
346#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
347#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000
348#define CONFIG_SYS_PCI_IO_BASE 0x00000000
349#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
350#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
351
352#define CONFIG_PCI_PNP
353
354#define CONFIG_PCI_SCAN_SHOW
355
356#endif
357
358
359#define CONFIG_HARD_I2C
360#define CONFIG_I2C_MULTI_BUS
361
362
363#define CONFIG_SYS_I2C_SPEED 100000
364#define CONFIG_SYS_I2C_SLAVE 0x7F
365#if 0
366#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}
367#endif
368
369
370
371
372#undef CONFIG_FSL_IIM
373
374
375
376
377
378#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
379#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
380#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
381#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
382
383
384
385
386#define CONFIG_MPC512x_FEC 1
387#define CONFIG_PHY_ADDR 0x17
388#define CONFIG_MII 1
389#define CONFIG_FEC_AN_TIMEOUT 1
390#define CONFIG_HAS_ETH0
391
392
393
394
395#define CONFIG_ENV_IS_IN_FLASH 1
396
397#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
398 CONFIG_SYS_MONITOR_LEN)
399#define CONFIG_ENV_SIZE 0x2000
400#define CONFIG_ENV_SECT_SIZE 0x20000
401
402
403#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
404 CONFIG_ENV_SECT_SIZE)
405#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
406
407#define CONFIG_LOADS_ECHO 1
408#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
409
410#include <config_cmd_default.h>
411
412#define CONFIG_CMD_ASKENV
413#define CONFIG_CMD_DHCP
414#define CONFIG_CMD_EEPROM
415#undef CONFIG_CMD_FUSE
416#define CONFIG_CMD_I2C
417#undef CONFIG_CMD_IDE
418#define CONFIG_CMD_JFFS2
419#define CONFIG_CMD_MII
420#define CONFIG_CMD_NFS
421#define CONFIG_CMD_PING
422#define CONFIG_CMD_REGINFO
423
424#if defined(CONFIG_PCI)
425#define CONFIG_CMD_PCI
426#endif
427
428#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
429#define CONFIG_DOS_PARTITION
430#define CONFIG_MAC_PARTITION
431#define CONFIG_ISO_PARTITION
432#endif
433
434
435
436
437#define CONFIG_CMD_MTDPARTS
438#define CONFIG_MTD_DEVICE
439#define CONFIG_FLASH_CFI_MTD
440#define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand"
441
442
443
444
445
446
447
448
449
450
451
452
453#define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \
454 "16m(rootfs)," \
455 "4m(kernel)," \
456 "768k(u-boot)," \
457 "256k(dtb);" \
458 "mpc5121.nand:-(data)"
459
460
461
462
463
464
465
466
467#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
468
469
470
471
472#define CONFIG_SYS_LONGHELP
473#define CONFIG_SYS_LOAD_ADDR 0x2000000
474
475#ifdef CONFIG_CMD_KGDB
476# define CONFIG_SYS_CBSIZE 1024
477#else
478# define CONFIG_SYS_CBSIZE 256
479#endif
480
481
482#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
483 sizeof(CONFIG_SYS_PROMPT) + 16)
484
485#define CONFIG_SYS_MAXARGS 32
486
487#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
488
489
490
491
492
493
494#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
495
496
497#define CONFIG_SYS_DCACHE_SIZE 32768
498#define CONFIG_SYS_CACHELINE_SIZE 32
499#ifdef CONFIG_CMD_KGDB
500#define CONFIG_SYS_CACHELINE_SHIFT 5
501#endif
502
503#define CONFIG_SYS_HID0_INIT 0x000000000
504#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
505 HID0_ICE)
506#define CONFIG_SYS_HID2 HID2_HBE
507
508#define CONFIG_HIGH_BATS 1
509
510#ifdef CONFIG_CMD_KGDB
511#define CONFIG_KGDB_BAUDRATE 230400
512#endif
513
514
515
516
517#define CONFIG_ENV_OVERWRITE
518#define CONFIG_TIMESTAMP
519
520#define CONFIG_HOSTNAME aria
521#define CONFIG_BOOTFILE "aria/uImage"
522#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
523
524#define CONFIG_LOADADDR 400000
525
526#define CONFIG_BOOTDELAY 5
527#undef CONFIG_BOOTARGS
528
529#define CONFIG_BAUDRATE 115200
530
531#define CONFIG_PREBOOT "echo;" \
532 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
533 "echo"
534
535#define CONFIG_EXTRA_ENV_SETTINGS \
536 "u-boot_addr_r=200000\0" \
537 "kernel_addr_r=600000\0" \
538 "fdt_addr_r=880000\0" \
539 "ramdisk_addr_r=900000\0" \
540 "u-boot_addr=FFF00000\0" \
541 "kernel_addr=FFB00000\0" \
542 "fdt_addr=FFFC0000\0" \
543 "ramdisk_addr=FEB00000\0" \
544 "ramdiskfile=aria/uRamdisk\0" \
545 "u-boot=aria/u-boot.bin\0" \
546 "fdtfile=aria/aria.dtb\0" \
547 "netdev=eth0\0" \
548 "consdev=ttyPSC0\0" \
549 "nfsargs=setenv bootargs root=/dev/nfs rw " \
550 "nfsroot=${serverip}:${rootpath}\0" \
551 "ramargs=setenv bootargs root=/dev/ram rw\0" \
552 "addip=setenv bootargs ${bootargs} " \
553 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
554 ":${hostname}:${netdev}:off panic=1\0" \
555 "addtty=setenv bootargs ${bootargs} " \
556 "console=${consdev},${baudrate}\0" \
557 "flash_nfs=run nfsargs addip addtty;" \
558 "bootm ${kernel_addr} - ${fdt_addr}\0" \
559 "flash_self=run ramargs addip addtty;" \
560 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
561 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
562 "tftp ${fdt_addr_r} ${fdtfile};" \
563 "run nfsargs addip addtty;" \
564 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
565 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
566 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
567 "tftp ${fdt_addr_r} ${fdtfile};" \
568 "run ramargs addip addtty;" \
569 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
570 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
571 "update=protect off ${u-boot_addr} +${filesize};" \
572 "era ${u-boot_addr} +${filesize};" \
573 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
574 "upd=run load update\0" \
575 ""
576
577#define CONFIG_BOOTCOMMAND "run flash_self"
578
579#define CONFIG_OF_LIBFDT 1
580#define CONFIG_OF_BOARD_SETUP 1
581#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
582
583#define OF_CPU "PowerPC,5121@0"
584#define OF_SOC_COMPAT "fsl,mpc5121-immr"
585#define OF_TBCLK (bd->bi_busfreq / 4)
586#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
587
588
589
590
591
592
593#undef CONFIG_IDE_8xx_PCCARD
594#undef CONFIG_IDE_8xx_DIRECT
595#undef CONFIG_IDE_LED
596
597#define CONFIG_IDE_RESET
598#define CONFIG_IDE_PREINIT
599
600#define CONFIG_SYS_IDE_MAXBUS 1
601#define CONFIG_SYS_IDE_MAXDEVICE 2
602
603#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
604#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
605
606
607#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
608
609
610#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
611
612
613#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
614
615
616#define CONFIG_SYS_ATA_STRIDE 4
617
618#define ATA_BASE_ADDR get_pata_base()
619
620
621
622
623#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
624#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
625#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
626#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
627#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
628#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
629#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
630#define FSL_ATA_CTRL_IORDY_EN 0x01000000
631
632
633#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
634 CLOCK_SCCR1_LPC_EN | \
635 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
636 CLOCK_SCCR1_PSCFIFO_EN | \
637 CLOCK_SCCR1_DDR_EN | \
638 CLOCK_SCCR1_FEC_EN | \
639 CLOCK_SCCR1_NFC_EN | \
640 CLOCK_SCCR1_PATA_EN | \
641 CLOCK_SCCR1_PCI_EN | \
642 CLOCK_SCCR1_TPR_EN)
643
644#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
645 CLOCK_SCCR2_SPDIF_EN | \
646 CLOCK_SCCR2_DIU_EN | \
647 CLOCK_SCCR2_I2C_EN)
648
649#endif
650