1/* 2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 3 * 4 * Copyright (C) 2008 Lyrtech <www.lyrtech.com> 5 * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10#ifndef __CONFIG_H 11#define __CONFIG_H 12 13/* Board */ 14#define SFFSDR 15#define CONFIG_SYS_NAND_LARGEPAGE 16#define CONFIG_SYS_USE_NAND 17#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */ 18/* SoC Configuration */ 19#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ 20#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ 21#define CONFIG_SOC_DM644X 22/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ 23#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 24#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 25#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 26#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 27/* Memory Info */ 28#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ 29#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ 30#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ 31#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 32#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ 33#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ 34#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ 35/* Serial Driver info */ 36#define CONFIG_SYS_NS16550 37#define CONFIG_SYS_NS16550_SERIAL 38#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ 39#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ 40#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */ 41#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 42#define CONFIG_BAUDRATE 115200 /* Default baud rate */ 43/* I2C Configuration */ 44#define CONFIG_SYS_I2C 45#define CONFIG_SYS_I2C_DAVINCI 46#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ 47#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 48/* Network & Ethernet Configuration */ 49#define CONFIG_DRIVER_TI_EMAC 50#define CONFIG_MII 51#define CONFIG_BOOTP_DNS 52#define CONFIG_BOOTP_DNS2 53#define CONFIG_BOOTP_SEND_HOSTNAME 54#define CONFIG_NET_RETRY_COUNT 10 55#define CONFIG_OVERWRITE_ETHADDR_ONCE 56/* Flash & Environment */ 57#undef CONFIG_ENV_IS_IN_FLASH 58#define CONFIG_SYS_NO_FLASH 59#define CONFIG_NAND_DAVINCI 60#define CONFIG_SYS_NAND_CS 2 61#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ 62#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ 63#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 64#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ 65#define CONFIG_SYS_NAND_BASE 0x02000000 66#define CONFIG_SYS_NAND_HW_ECC 67#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 68#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 69/* I2C switch definitions for PCA9543 chip */ 70#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70 71#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */ 72#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ 73/* U-Boot general configuration */ 74#define CONFIG_MISC_INIT_R 75#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */ 76#define CONFIG_BOOTFILE "uImage" /* Boot file name */ 77#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */ 78#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 79#define CONFIG_SYS_PBSIZE \ 80 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */ 81#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 82#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 83#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel 84 * load address. */ 85#define CONFIG_VERSION_VARIABLE 86#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, 87 * may be later */ 88#define CONFIG_SYS_HUSH_PARSER 89#define CONFIG_CMDLINE_EDITING 90#define CONFIG_SYS_LONGHELP 91#define CONFIG_CRC32_VERIFY 92#define CONFIG_MX_CYCLIC 93/* Linux Information */ 94#define LINUX_BOOT_PARAM_ADDR 0x80000100 95#define CONFIG_CMDLINE_TAG 96#define CONFIG_SETUP_MEMORY_TAGS 97#define CONFIG_BOOTARGS \ 98 "mem=56M " \ 99 "console=ttyS0,115200n8 " \ 100 "root=/dev/nfs rw noinitrd ip=dhcp " \ 101 "nfsroot=${serverip}:/nfsroot/sffsdr " \ 102 "eth0=${ethaddr}" 103#define CONFIG_BOOTCOMMAND \ 104 "nand read 87A00000 100000 300000;" \ 105 "bootelf 87A00000" 106/* U-Boot commands */ 107#include <config_cmd_default.h> 108#define CONFIG_CMD_ASKENV 109#define CONFIG_CMD_DHCP 110#define CONFIG_CMD_DIAG 111#define CONFIG_CMD_I2C 112#define CONFIG_CMD_MII 113#define CONFIG_CMD_PING 114#define CONFIG_CMD_SAVES 115#define CONFIG_CMD_NAND 116#define CONFIG_CMD_EEPROM 117#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */ 118#undef CONFIG_CMD_BDI 119#undef CONFIG_CMD_FPGA 120#undef CONFIG_CMD_SETGETDCR 121#undef CONFIG_CMD_FLASH 122#undef CONFIG_CMD_IMLS 123 124#ifdef CONFIG_CMD_BDI 125#define CONFIG_CLOCKS 126#endif 127 128#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ 129 130#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 131#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 132#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ 133 CONFIG_SYS_INIT_RAM_SIZE - \ 134 GENERATED_GBL_DATA_SIZE) 135 136#endif /* __CONFIG_H */ 137