LXR uboot/include/configs/dlvision-10g.h

   1/*
   2 * (C) Copyright 2010
   3 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef __CONFIG_H
   9#define __CONFIG_H
  10
  11#define CONFIG_405EP            1       /* this is a PPC405 CPU */
  12#define CONFIG_DLVISION_10G     1       /*  on a DLVision-10G board */
  13
  14#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15
  16/*
  17 * Include common defines/options for all AMCC eval boards
  18 */
  19#define CONFIG_HOSTNAME         dlvsion-10g
  20#define CONFIG_IDENT_STRING     " dlvision-10g 0.06"
  21#include "amcc-common.h"
  22
  23#define CONFIG_BOARD_EARLY_INIT_F
  24#define CONFIG_BOARD_EARLY_INIT_R
  25#define CONFIG_MISC_INIT_R
  26#define CONFIG_LAST_STAGE_INIT
  27#define CONFIG_SYS_GENERIC_BOARD
  28
  29#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  30
  31#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
  32#define CONFIG_AUTOBOOT_KEYED          /* use key strings to stop autoboot */
  33#define CONFIG_AUTOBOOT_STOP_STR " "
  34
  35/*
  36 * Configure PLL
  37 */
  38#define PLLMR0_DEFAULT PLLMR0_266_133_66
  39#define PLLMR1_DEFAULT PLLMR1_266_133_66
  40
  41/* new uImage format support */
  42#define CONFIG_FIT
  43#define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
  44#define CONFIG_FIT_DISABLE_SHA256
  45
  46#define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  47
  48/*
  49 * Default environment variables
  50 */
  51#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  52        CONFIG_AMCC_DEF_ENV                                             \
  53        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  54        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  55        "kernel_addr=fc000000\0"                                        \
  56        "fdt_addr=fc1e0000\0"                                           \
  57        "ramdisk_addr=fc200000\0"                                       \
  58        ""
  59
  60#define CONFIG_PHY_ADDR         4       /* PHY address                  */
  61#define CONFIG_HAS_ETH0
  62#define CONFIG_HAS_ETH1
  63#define CONFIG_PHY1_ADDR        0xc     /* EMAC1 PHY address            */
  64#define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ
  65
  66/*
  67 * Commands additional to the ones defined in amcc-common.h
  68 */
  69#define CONFIG_CMD_DTT
  70#undef CONFIG_CMD_DHCP
  71#undef CONFIG_CMD_DIAG
  72#undef CONFIG_CMD_EEPROM
  73#undef CONFIG_CMD_ELF
  74#undef CONFIG_CMD_I2C
  75#undef CONFIG_CMD_IRQ
  76#undef CONFIG_CMD_NFS
  77
  78/*
  79 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  80 */
  81#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  82
  83/* SDRAM timings used in datasheet */
  84#define CONFIG_SYS_SDRAM_CL             3       /* CAS latency */
  85#define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  86#define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE period */
  87#define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  88#define CONFIG_SYS_SDRAM_tRFC          66       /* Auto refresh period */
  89
  90/*
  91 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  92 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  93 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
  94 * The Linux BASE_BAUD define should match this configuration.
  95 *    baseBaud = cpuClock/(uartDivisor*16)
  96 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  97 * set Linux BASE_BAUD to 403200.
  98 */
  99#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 100#undef  CONFIG_SYS_EXT_SERIAL_CLOCK     /* external serial clock */
 101#undef  CONFIG_SYS_405_UART_ERRATA_59   /* 405GP/CR Rev. D silicon */
 102#define CONFIG_SYS_BASE_BAUD            691200
 103
 104/*
 105 * I2C stuff
 106 */
 107#define CONFIG_SYS_I2C_PPC4XX
 108#define CONFIG_SYS_I2C_PPC4XX_CH0
 109#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 110#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 111
 112#define CONFIG_SYS_I2C_IHS
 113#define CONFIG_SYS_I2C_IHS_CH0
 114#define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 115#define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 116#define CONFIG_SYS_I2C_IHS_CH1
 117#define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 118#define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 119
 120#define CONFIG_SYS_SPD_BUS_NUM          2
 121
 122/* Temp sensor/hwmon/dtt */
 123#define CONFIG_SYS_DTT_BUS_NUM  2
 124#define CONFIG_DTT_LM63         1       /* National LM63        */
 125#define CONFIG_DTT_SENSORS      { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
 126#define CONFIG_DTT_PWM_LOOKUPTABLE      \
 127                { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
 128                  { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
 129#define CONFIG_DTT_TACH_LIMIT   0xa10
 130
 131#define CONFIG_SYS_ICS8N3QV01_I2C       {0, 1}
 132#define CONFIG_SYS_SIL1178_I2C          {0, 1}
 133
 134/* EBC peripherals */
 135
 136#define CONFIG_SYS_FLASH_BASE           0xFC000000
 137#define CONFIG_SYS_FPGA0_BASE           0x7f100000
 138#define CONFIG_SYS_FPGA1_BASE           0x7f200000
 139#define CONFIG_SYS_LATCH_BASE           0x7f300000
 140
 141#define CONFIG_SYS_FPGA_BASE(k) \
 142        (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
 143
 144#define CONFIG_SYS_FPGA_DONE(k) \
 145        (k ? 0x2000 : 0x1000)
 146
 147#define CONFIG_SYS_FPGA_COUNT           2
 148
 149#define CONFIG_SYS_FPGA_PTR { \
 150        (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
 151        (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
 152
 153#define CONFIG_SYS_FPGA_COMMON
 154
 155#define CONFIG_SYS_LATCH0_RESET         0xffff
 156#define CONFIG_SYS_LATCH0_BOOT          0xffff
 157#define CONFIG_SYS_LATCH1_RESET         0xffbf
 158#define CONFIG_SYS_LATCH1_BOOT          0xffff
 159
 160#define CONFIG_SYS_FPGA_NO_RFL_HI
 161
 162/*
 163 * FLASH organization
 164 */
 165#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 166#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 167
 168#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 169
 170#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 171#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 172
 173#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 174#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 175
 176#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buff'd writes */
 177
 178#define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 179#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* no warn upon unknown flash */
 180
 181#ifdef CONFIG_ENV_IS_IN_FLASH
 182#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 183#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 184#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector */
 185
 186/* Address and size of Redundant Environment Sector     */
 187#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 188#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 189#endif
 190
 191/*
 192 * PPC405 GPIO Configuration
 193 */
 194#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO     Alternate1      */ \
 195{ \
 196/* GPIO Core 0 */ \
 197{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast */ \
 198{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E */ \
 199{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E */ \
 200{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O */ \
 201{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O */ \
 202{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3 */ \
 203{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4 */ \
 204{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7   TS5 */ \
 205{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6 */ \
 206{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk */ \
 207{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1 */ \
 208{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2 */ \
 209{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3 */ \
 210{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4 */ \
 211{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03 */ \
 212{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04 */ \
 213{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05 */ \
 214{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0 */ \
 215{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1 */ \
 216{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2 */ \
 217{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3 */ \
 218{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4 */ \
 219{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5 */ \
 220{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6 */ \
 221{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD */ \
 222{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR */ \
 223{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI */ \
 224{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR */ \
 225{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx */ \
 226{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx */ \
 227{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 228{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 229} \
 230}
 231
 232/*
 233 * Definitions for initial stack pointer and data area (in data cache)
 234 */
 235/* use on chip memory (OCM) for temperary stack until sdram is tested */
 236#define CONFIG_SYS_TEMP_STACK_OCM       1
 237
 238/* On Chip Memory location */
 239#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 240#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 241#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 242#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
 243
 244#define CONFIG_SYS_GBL_DATA_OFFSET \
 245        (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
 246#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 247
 248/*
 249 * External Bus Controller (EBC) Setup
 250 */
 251
 252/* Memory Bank 0 (NOR-flash) */
 253#define CONFIG_SYS_EBC_PB0AP    (EBC_BXAP_BME_ENABLED           |       \
 254                                 EBC_BXAP_FWT_ENCODE(8)         |       \
 255                                 EBC_BXAP_BWT_ENCODE(7)         |       \
 256                                 EBC_BXAP_BCE_DISABLE           |       \
 257                                 EBC_BXAP_BCT_2TRANS            |       \
 258                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 259                                 EBC_BXAP_OEN_ENCODE(2)         |       \
 260                                 EBC_BXAP_WBN_ENCODE(2)         |       \
 261                                 EBC_BXAP_WBF_ENCODE(2)         |       \
 262                                 EBC_BXAP_TH_ENCODE(4)          |       \
 263                                 EBC_BXAP_RE_DISABLED           |       \
 264                                 EBC_BXAP_SOR_NONDELAYED        |       \
 265                                 EBC_BXAP_BEM_WRITEONLY         |       \
 266                                 EBC_BXAP_PEN_DISABLED)
 267#define CONFIG_SYS_EBC_PB0CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
 268                                 EBC_BXCR_BS_64MB               |       \
 269                                 EBC_BXCR_BU_RW                 |       \
 270                                 EBC_BXCR_BW_16BIT)
 271
 272/* Memory Bank 1 (FPGA0) */
 273#define CONFIG_SYS_EBC_PB1AP    (EBC_BXAP_BME_DISABLED          |       \
 274                                 EBC_BXAP_TWT_ENCODE(5)         |       \
 275                                 EBC_BXAP_BCE_DISABLE           |       \
 276                                 EBC_BXAP_BCT_2TRANS            |       \
 277                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 278                                 EBC_BXAP_OEN_ENCODE(2)         |       \
 279                                 EBC_BXAP_WBN_ENCODE(1)         |       \
 280                                 EBC_BXAP_WBF_ENCODE(1)         |       \
 281                                 EBC_BXAP_TH_ENCODE(0)          |       \
 282                                 EBC_BXAP_RE_DISABLED           |       \
 283                                 EBC_BXAP_SOR_NONDELAYED        |       \
 284                                 EBC_BXAP_BEM_WRITEONLY         |       \
 285                                 EBC_BXAP_PEN_DISABLED)
 286#define CONFIG_SYS_EBC_PB1CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
 287                                 EBC_BXCR_BS_1MB                |       \
 288                                 EBC_BXCR_BU_RW                 |       \
 289                                 EBC_BXCR_BW_16BIT)
 290
 291/* Memory Bank 2 (FPGA1) */
 292#define CONFIG_SYS_EBC_PB2AP    (EBC_BXAP_BME_DISABLED          |       \
 293                                 EBC_BXAP_TWT_ENCODE(6)         |       \
 294                                 EBC_BXAP_BCE_DISABLE           |       \
 295                                 EBC_BXAP_BCT_2TRANS            |       \
 296                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 297                                 EBC_BXAP_OEN_ENCODE(2)         |       \
 298                                 EBC_BXAP_WBN_ENCODE(1)         |       \
 299                                 EBC_BXAP_WBF_ENCODE(1)         |       \
 300                                 EBC_BXAP_TH_ENCODE(0)          |       \
 301                                 EBC_BXAP_RE_DISABLED           |       \
 302                                 EBC_BXAP_SOR_NONDELAYED        |       \
 303                                 EBC_BXAP_BEM_WRITEONLY         |       \
 304                                 EBC_BXAP_PEN_DISABLED)
 305#define CONFIG_SYS_EBC_PB2CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
 306                                 EBC_BXCR_BS_1MB                |       \
 307                                 EBC_BXCR_BU_RW                 |       \
 308                                 EBC_BXCR_BW_16BIT)
 309
 310/* Memory Bank 3 (Latches) */
 311#define CONFIG_SYS_EBC_PB3AP    (EBC_BXAP_BME_ENABLED           |       \
 312                                 EBC_BXAP_FWT_ENCODE(8)         |       \
 313                                 EBC_BXAP_BWT_ENCODE(4)         |       \
 314                                 EBC_BXAP_BCE_DISABLE           |       \
 315                                 EBC_BXAP_BCT_2TRANS            |       \
 316                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 317                                 EBC_BXAP_OEN_ENCODE(1)         |       \
 318                                 EBC_BXAP_WBN_ENCODE(1)         |       \
 319                                 EBC_BXAP_WBF_ENCODE(1)         |       \
 320                                 EBC_BXAP_TH_ENCODE(2)          |       \
 321                                 EBC_BXAP_RE_DISABLED           |       \
 322                                 EBC_BXAP_SOR_NONDELAYED        |       \
 323                                 EBC_BXAP_BEM_WRITEONLY         |       \
 324                                 EBC_BXAP_PEN_DISABLED)
 325#define CONFIG_SYS_EBC_PB3CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
 326                                 EBC_BXCR_BS_1MB                |       \
 327                                 EBC_BXCR_BU_RW                 |       \
 328                                 EBC_BXCR_BW_16BIT)
 329
 330/*
 331 * OSD Setup
 332 */
 333#define CONFIG_SYS_MPC92469AC
 334#define CONFIG_SYS_OSD_SCREENS          CONFIG_SYS_FPGA_COUNT
 335
 336#endif  /* __CONFIG_H */
 337