1/* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the Freescale i.MX6Q SabreAuto board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __MX6QSABREAUTO_CONFIG_H 10#define __MX6QSABREAUTO_CONFIG_H 11 12#define CONFIG_MACH_TYPE 3529 13#define CONFIG_MXC_UART_BASE UART4_BASE 14#define CONFIG_CONSOLE_DEV "ttymxc3" 15#if defined CONFIG_MX6Q 16#define CONFIG_DEFAULT_FDT_FILE "imx6q-sabreauto.dtb" 17#elif defined CONFIG_MX6DL 18#define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabreauto.dtb" 19#endif 20#define CONFIG_MMCROOT "/dev/mmcblk0p2" 21#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) 22 23/* USB Configs */ 24#define CONFIG_CMD_USB 25#define CONFIG_USB_EHCI 26#define CONFIG_USB_EHCI_MX6 27#define CONFIG_USB_STORAGE 28#define CONFIG_USB_HOST_ETHER 29#define CONFIG_USB_ETHER_ASIX 30#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 31#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 32#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 33#define CONFIG_MXC_USB_FLAGS 0 34 35#define CONFIG_PCA953X 36#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } 37 38#include "mx6sabre_common.h" 39 40#undef CONFIG_SYS_NO_FLASH 41#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR 42#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) 43#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 44#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 45#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ 46#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ 47#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ 48#define CONFIG_SYS_FLASH_EMPTY_INFO 49 50#define CONFIG_SYS_FSL_USDHC_NUM 2 51#if defined(CONFIG_ENV_IS_IN_MMC) 52#define CONFIG_SYS_MMC_ENV_DEV 0 53#endif 54 55/* I2C Configs */ 56#define CONFIG_CMD_I2C 57#define CONFIG_SYS_I2C 58#define CONFIG_SYS_I2C_MXC 59#define CONFIG_SYS_I2C_SPEED 100000 60 61/* NAND flash command */ 62#define CONFIG_CMD_NAND 63#define CONFIG_CMD_NAND_TRIMFFS 64 65/* NAND stuff */ 66#define CONFIG_NAND_MXS 67#define CONFIG_SYS_MAX_NAND_DEVICE 1 68#define CONFIG_SYS_NAND_BASE 0x40000000 69#define CONFIG_SYS_NAND_5_ADDR_CYCLE 70#define CONFIG_SYS_NAND_ONFI_DETECTION 71 72/* DMA stuff, needed for GPMI/MXS NAND support */ 73#define CONFIG_APBH_DMA 74#define CONFIG_APBH_DMA_BURST 75#define CONFIG_APBH_DMA_BURST8 76 77/* PMIC */ 78#define CONFIG_POWER 79#define CONFIG_POWER_I2C 80#define CONFIG_POWER_PFUZE100 81#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 82 83#endif /* __MX6QSABREAUTO_CONFIG_H */ 84