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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14
15#define CONFIG_405EP 1
16#define CONFIG_TAIHU 1
17
18#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
19
20
21
22
23#define CONFIG_HOSTNAME taihu
24#include "amcc-common.h"
25
26#define CONFIG_BOARD_EARLY_INIT_F 1
27
28#define CONFIG_SYS_CLK_FREQ 33000000
29
30#define CONFIG_NO_SERIAL_EEPROM
31
32
33#ifdef CONFIG_NO_SERIAL_EEPROM
34
35
36
37
38
39
40
41#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
42 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
43 PLL_MALDIV_1 | PLL_PCIDIV_3)
44#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
45 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
46 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
47#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
48 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
49 PLL_MALDIV_1 | PLL_PCIDIV_1)
50#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
51 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
52 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
53
54#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
55#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
56#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
57#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
58
59#endif
60
61
62#define CONFIG_ENV_IS_IN_FLASH 1
63
64
65
66
67#define CONFIG_EXTRA_ENV_SETTINGS \
68 CONFIG_AMCC_DEF_ENV \
69 CONFIG_AMCC_DEF_ENV_PPC \
70 CONFIG_AMCC_DEF_ENV_NOR_UPD \
71 "kernel_addr=FC000000\0" \
72 "ramdisk_addr=FC180000\0" \
73 ""
74
75#define CONFIG_PHY_ADDR 0x14
76#define CONFIG_HAS_ETH0
77#define CONFIG_HAS_ETH1
78#define CONFIG_PHY1_ADDR 0x10
79#define CONFIG_PHY_RESET 1
80
81
82
83
84#define CONFIG_CMD_CACHE
85#define CONFIG_CMD_PCI
86#define CONFIG_CMD_SDRAM
87#define CONFIG_CMD_SPI
88
89#undef CONFIG_SPD_EEPROM
90#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000
91#define CONFIG_SYS_SDRAM_BANKS 2
92
93
94
95
96#define CONFIG_SDRAM_BANK0 1
97#define CONFIG_SDRAM_BANK1 1
98
99
100#define CONFIG_SYS_SDRAM_CL 3
101#define CONFIG_SYS_SDRAM_tRP 20
102#define CONFIG_SYS_SDRAM_tRC 66
103#define CONFIG_SYS_SDRAM_tRCD 20
104#define CONFIG_SYS_SDRAM_tRFC 66
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113
114
115#define CONFIG_CONS_INDEX 2
116#undef CONFIG_SYS_EXT_SERIAL_CLOCK
117#undef CONFIG_SYS_405_UART_ERRATA_59
118#define CONFIG_SYS_BASE_BAUD 691200
119
120
121
122
123
124#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
125
126#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
127#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6
128
129#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
130#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
131
132#define CONFIG_SOFT_SPI
133#define SPI_SCL spi_scl
134#define SPI_SDA spi_sda
135#define SPI_READ spi_read()
136#define SPI_DELAY udelay(2)
137#ifndef __ASSEMBLY__
138void spi_scl(int);
139void spi_sda(int);
140unsigned char spi_read(void);
141#endif
142
143
144#define CONFIG_DTT_DS1775 1
145#define CONFIG_DTT_SENSORS { 0 }
146#define CONFIG_SYS_I2C_DTT_ADDR 0x49
147
148
149
150
151
152#define PCI_HOST_ADAPTER 0
153#define PCI_HOST_FORCE 1
154#define PCI_HOST_AUTO 2
155
156#define CONFIG_PCI
157#define CONFIG_PCI_INDIRECT_BRIDGE
158#define CONFIG_PCI_HOST PCI_HOST_FORCE
159#define CONFIG_PCI_PNP
160
161#define CONFIG_PCI_SCAN_SHOW
162
163#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8
164#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe
165#define CONFIG_SYS_PCI_CLASSCODE 0x0600
166#define CONFIG_SYS_PCI_PTM1LA 0x00000000
167#define CONFIG_SYS_PCI_PTM1MS 0x80000001
168#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
169#define CONFIG_SYS_PCI_PTM2LA 0x00000000
170#define CONFIG_SYS_PCI_PTM2MS 0x00000000
171#define CONFIG_SYS_PCI_PTM2PCI 0x04000000
172#define CONFIG_EEPRO100 1
173
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176
177
178#define CONFIG_SYS_FLASH_BASE 0xFFE00000
179
180
181
182
183#define CONFIG_SYS_MAX_FLASH_BANKS 2
184#define CONFIG_SYS_MAX_FLASH_SECT 256
185
186#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
187#define CONFIG_SYS_FLASH_WRITE_TOUT 500
188
189#define CONFIG_SYS_FLASH_ADDR0 0x555
190#define CONFIG_SYS_FLASH_ADDR1 0x2aa
191#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
192
193#ifdef CONFIG_ENV_IS_IN_FLASH
194#define CONFIG_ENV_SECT_SIZE 0x10000
195#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
196#define CONFIG_ENV_SIZE 0x4000
197
198
199#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
200#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
201#endif
202
203
204
205
206#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000
207#define CONFIG_SYS_NVRAM_SIZE 0x1ff8
208
209#ifdef CONFIG_ENV_IS_IN_NVRAM
210#define CONFIG_ENV_SIZE 0x0ff8
211#define CONFIG_ENV_ADDR \
212 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
213#endif
214
215
216
217
218#define CONFIG_SYS_4xx_GPIO_TABLE { \
219{ \
220 \
221{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
222{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
223{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
224{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
225{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
226{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
227{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
228{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
229{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
230{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
231{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
232{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
233{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
234{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
235{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
236{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
237{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
238{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
239{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
240{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
241{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
242{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
243{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
244{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
245{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
246{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
247{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
248{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
249{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
250{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
251{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
252{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
253} \
254}
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260
261
262#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE
263#define FLASH_BASE1_PRELIM 0xFC000000
264
265
266
267
268
269#define CONFIG_SYS_TEMP_STACK_OCM 1
270
271
272#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
273#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
274#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
275#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
276
277#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
278#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
279
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282
283
284
285#define CONFIG_SYS_EBC_PB0AP 0x03815600
286#define CONFIG_SYS_EBC_PB0CR 0xFFE3A000
287
288
289#define CONFIG_SYS_EBC_PB1AP 0x05815600
290#define CONFIG_SYS_EBC_PB1CR 0xFC0BA000
291
292
293#define CONFIG_SYS_EBC_PB2AP 0x03016600
294#define CONFIG_SYS_EBC_PB2CR 0x50018000
295
296
297#define CONFIG_SYS_EBC_PB3AP 0x158FF600
298#define CONFIG_SYS_EBC_PB3CR 0x50118000
299
300
301#define CONFIG_SYS_EBC_PB4AP 0x158FF600
302#define CONFIG_SYS_EBC_PB4CR 0x5021A000
303
304#define CPLD_REG0_ADDR 0x50100000
305#define CPLD_REG1_ADDR 0x50100001
306
307#endif
308