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14#ifndef _VSC9953_H_
15#define _VSC9953_H_
16
17#include <config.h>
18#include <miiphy.h>
19#include <asm/types.h>
20#include <malloc.h>
21
22#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
23
24#define VSC9953_SYS_OFFSET 0x010000
25#define VSC9953_DEV_GMII_OFFSET 0x100000
26#define VSC9953_QSYS_OFFSET 0x200000
27#define VSC9953_ANA_OFFSET 0x280000
28#define VSC9953_DEVCPU_GCB 0x070000
29#define VSC9953_ES0 0x040000
30#define VSC9953_IS1 0x050000
31#define VSC9953_IS2 0x060000
32
33#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
34#define VSC9953_PHY_REGS_OFFST 0x0000AC
35
36#define CONFIG_VSC9953_SOFT_SWC_RST_ENA 0x00000001
37#define CONFIG_VSC9953_CORE_ENABLE 0x80
38#define CONFIG_VSC9953_MEM_ENABLE 0x40
39#define CONFIG_VSC9953_MEM_INIT 0x20
40
41#define CONFIG_VSC9953_PORT_ENA 0x00003a00
42#define CONFIG_VSC9953_MAC_ENA_CFG 0x00000011
43#define CONFIG_VSC9953_MAC_MODE_CFG 0x00000011
44#define CONFIG_VSC9953_MAC_IFG_CFG 0x00000515
45#define CONFIG_VSC9953_MAC_HDX_CFG 0x00001043
46#define CONFIG_VSC9953_CLOCK_CFG 0x00000001
47#define CONFIG_VSC9953_CLOCK_CFG_1000M 0x00000001
48#define CONFIG_VSC9953_PFC_FC 0x00000001
49#define CONFIG_VSC9953_PFC_FC_QSGMII 0x00000000
50#define CONFIG_VSC9953_MAC_FC_CFG 0x04700000
51#define CONFIG_VSC9953_MAC_FC_CFG_QSGMII 0x00700000
52#define CONFIG_VSC9953_PAUSE_CFG 0x001ffffe
53#define CONFIG_VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
54#define CONFIG_VSC9953_FRONT_PORT_MODE 0x00000000
55#define CONFIG_VSC9953_MAC_MAX_LEN 0x000005ee
56
57#define CONFIG_VSC9953_VCAP_MV_CFG 0x0000ffff
58#define CONFIG_VSC9953_VCAP_UPDATE_CTRL 0x01000004
59#define VSC9953_MAX_PORTS 10
60#define VSC9953_PORT_CHECK(port) \
61 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
62#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
63 ( \
64 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
65 ) ? 0 : 1 \
66)
67
68#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
69
70#define MIIMIND_OPR_PEND 0x00000004
71
72struct vsc9953_mdio_info {
73 struct vsc9953_mii_mng *regs;
74 char *name;
75};
76
77
78
79struct vsc9953_ana_port {
80 u32 vlan_cfg;
81 u32 drop_cfg;
82 u32 qos_cfg;
83 u32 vcap_cfg;
84 u32 vcap_s1_key_cfg[3];
85 u32 vcap_s2_cfg;
86 u32 qos_pcp_dei_map_cfg[16];
87 u32 cpu_fwd_cfg;
88 u32 cpu_fwd_bpdu_cfg;
89 u32 cpu_fwd_garp_cfg;
90 u32 cpu_fwd_ccm_cfg;
91 u32 port_cfg;
92 u32 pol_cfg;
93 u32 reserved[34];
94};
95
96struct vsc9953_ana_pol {
97 u32 pol_pir_cfg;
98 u32 pol_cir_cfg;
99 u32 pol_mode_cfg;
100 u32 pol_pir_state;
101 u32 pol_cir_state;
102 u32 reserved1[3];
103};
104
105struct vsc9953_ana_ana_tables {
106 u32 entry_lim[11];
107 u32 an_moved;
108 u32 mach_data;
109 u32 macl_data;
110 u32 mac_access;
111 u32 mact_indx;
112 u32 vlan_access;
113 u32 vlan_tidx;
114};
115
116struct vsc9953_ana_ana {
117 u32 adv_learn;
118 u32 vlan_mask;
119 u32 anag_efil;
120 u32 an_events;
121 u32 storm_limit_burst;
122 u32 storm_limit_cfg[4];
123 u32 isolated_prts;
124 u32 community_ports;
125 u32 auto_age;
126 u32 mac_options;
127 u32 learn_disc;
128 u32 agen_ctrl;
129 u32 mirror_ports;
130 u32 emirror_ports;
131 u32 flooding;
132 u32 flooding_ipmc;
133 u32 sflow_cfg[11];
134 u32 port_mode[12];
135};
136
137struct vsc9953_ana_pgid {
138 u32 port_grp_id[91];
139};
140
141struct vsc9953_ana_pfc {
142 u32 pfc_cfg;
143 u32 reserved1[15];
144};
145
146struct vsc9953_ana_pol_misc {
147 u32 pol_flowc[10];
148 u32 reserved1[17];
149 u32 pol_hyst;
150};
151
152struct vsc9953_ana_common {
153 u32 aggr_cfg;
154 u32 cpuq_cfg;
155 u32 cpuq_8021_cfg;
156 u32 dscp_cfg;
157 u32 dscp_rewr_cfg;
158 u32 vcap_rng_type_cfg;
159 u32 vcap_rng_val_cfg;
160 u32 discard_cfg;
161 u32 fid_cfg;
162};
163
164struct vsc9953_analyzer {
165 struct vsc9953_ana_port port[11];
166 u32 reserved1[9536];
167 struct vsc9953_ana_pol pol[164];
168 struct vsc9953_ana_ana_tables ana_tables;
169 u32 reserved2[14];
170 struct vsc9953_ana_ana ana;
171 u32 reserved3[22];
172 struct vsc9953_ana_pgid port_id_tbl;
173 u32 reserved4[549];
174 struct vsc9953_ana_pfc pfc[10];
175 struct vsc9953_ana_pol_misc pol_misc;
176 u32 reserved5[196];
177 struct vsc9953_ana_common common;
178};
179
180
181
182
183struct vsc9953_dev_gmii_port_mode {
184 u32 clock_cfg;
185 u32 port_misc;
186 u32 reserved1;
187 u32 eee_cfg;
188};
189
190struct vsc9953_dev_gmii_mac_cfg_status {
191 u32 mac_ena_cfg;
192 u32 mac_mode_cfg;
193 u32 mac_maxlen_cfg;
194 u32 mac_tags_cfg;
195 u32 mac_adv_chk_cfg;
196 u32 mac_ifg_cfg;
197 u32 mac_hdx_cfg;
198 u32 mac_fc_mac_low_cfg;
199 u32 mac_fc_mac_high_cfg;
200 u32 mac_sticky;
201};
202
203struct vsc9953_dev_gmii {
204 struct vsc9953_dev_gmii_port_mode port_mode;
205 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
206};
207
208
209
210
211
212struct vsc9953_qsys_hsch {
213 u32 cir_cfg;
214 u32 reserved1;
215 u32 se_cfg;
216 u32 se_dwrr_cfg[8];
217 u32 cir_state;
218 u32 reserved2[20];
219};
220
221struct vsc9953_qsys_sys {
222 u32 port_mode[12];
223 u32 switch_port_mode[11];
224 u32 stat_cnt_cfg;
225 u32 eee_cfg[10];
226 u32 eee_thrs;
227 u32 igr_no_sharing;
228 u32 egr_no_sharing;
229 u32 sw_status[11];
230 u32 ext_cpu_cfg;
231 u32 cpu_group_map;
232 u32 reserved1[23];
233};
234
235struct vsc9953_qsys_qos_cfg {
236 u32 red_profile[16];
237 u32 res_qos_mode;
238};
239
240struct vsc9953_qsys_drop_cfg {
241 u32 egr_drop_mode;
242};
243
244struct vsc9953_qsys_mmgt {
245 u32 eq_cntrl;
246 u32 reserved1;
247};
248
249struct vsc9953_qsys_hsch_misc {
250 u32 hsch_misc_cfg;
251 u32 reserved1[546];
252};
253
254struct vsc9953_qsys_res_ctrl {
255 u32 res_cfg;
256 u32 res_stat;
257
258};
259
260struct vsc9953_qsys_reg {
261 struct vsc9953_qsys_hsch hsch[108];
262 struct vsc9953_qsys_sys sys;
263 struct vsc9953_qsys_qos_cfg qos_cfg;
264 struct vsc9953_qsys_drop_cfg drop_cfg;
265 struct vsc9953_qsys_mmgt mmgt;
266 struct vsc9953_qsys_hsch_misc hsch_misc;
267 struct vsc9953_qsys_res_ctrl res_ctrl[1024];
268};
269
270
271
272
273
274struct vsc9953_sys_stat {
275 u32 rx_cntrs[64];
276 u32 tx_cntrs[64];
277 u32 drop_cntrs[64];
278 u32 reserved1[6];
279};
280
281struct vsc9953_sys_sys {
282 u32 reset_cfg;
283 u32 reserved1;
284 u32 vlan_etype_cfg;
285 u32 port_mode[12];
286 u32 front_port_mode[10];
287 u32 frame_aging;
288 u32 stat_cfg;
289 u32 reserved2[50];
290};
291
292struct vsc9953_sys_pause_cfg {
293 u32 pause_cfg[11];
294 u32 pause_tot_cfg;
295 u32 tail_drop_level[11];
296 u32 tot_tail_drop_lvl;
297 u32 mac_fc_cfg[10];
298};
299
300struct vsc9953_sys_mmgt {
301 u16 free_cnt;
302};
303
304struct vsc9953_system_reg {
305 struct vsc9953_sys_stat stat;
306 struct vsc9953_sys_sys sys;
307 struct vsc9953_sys_pause_cfg pause_cfg;
308 struct vsc9953_sys_mmgt mmgt;
309};
310
311
312
313
314
315
316struct vsc9953_chip_regs {
317 u32 chipd_id;
318 u32 gpr;
319 u32 soft_rst;
320};
321
322struct vsc9953_gpio {
323 u32 gpio_out_set[10];
324 u32 gpio_out_clr[10];
325 u32 gpio_out[10];
326 u32 gpio_in[10];
327};
328
329struct vsc9953_mii_mng {
330 u32 miimstatus;
331 u32 reserved1;
332 u32 miimcmd;
333 u32 miimdata;
334 u32 miimcfg;
335 u32 miimscan_0;
336 u32 miimscan_1;
337 u32 miiscan_lst_rslts;
338 u32 miiscan_lst_rslts_valid;
339};
340
341struct vsc9953_mii_read_scan {
342 u32 mii_scan_results_sticky[2];
343};
344
345struct vsc9953_devcpu_gcb {
346 struct vsc9953_chip_regs chip_regs;
347 struct vsc9953_gpio gpio;
348 struct vsc9953_mii_mng mii_mng[2];
349 struct vsc9953_mii_read_scan mii_read_scan;
350};
351
352
353
354
355
356struct vsc9953_vcap_core_cfg {
357 u32 vcap_update_ctrl;
358 u32 vcap_mv_cfg;
359};
360
361struct vsc9953_vcap {
362struct vsc9953_vcap_core_cfg vcap_core_cfg;
363};
364
365
366
367#define VSC9953_PORT_INFO_INITIALIZER(idx) \
368{ \
369 .enabled = 0, \
370 .phyaddr = 0, \
371 .index = idx, \
372 .phy_regs = NULL, \
373 .enet_if = PHY_INTERFACE_MODE_NONE, \
374 .bus = NULL, \
375 .phydev = NULL, \
376}
377
378
379struct vsc9953_port_info {
380 u8 enabled;
381 u8 phyaddr;
382 int index;
383 void *phy_regs;
384 phy_interface_t enet_if;
385 struct mii_dev *bus;
386 struct phy_device *phydev;
387};
388
389
390struct vsc9953_info {
391 struct vsc9953_port_info port[VSC9953_MAX_PORTS];
392};
393
394void vsc9953_init(bd_t *bis);
395
396void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus);
397void vsc9953_port_info_set_phy_address(int port, int address);
398void vsc9953_port_enable(int port);
399void vsc9953_port_disable(int port);
400void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int);
401
402#endif
403
