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8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/arch/gpio.h>
12
13void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
14{
15 u32 index = GPIO_CFG_INDEX(bank_offset);
16 u32 offset = GPIO_CFG_OFFSET(bank_offset);
17
18 clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
19}
20
21void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
22{
23 u32 bank = GPIO_BANK(pin);
24 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
25
26 sunxi_gpio_set_cfgbank(pio, pin, val);
27}
28
29int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
30{
31 u32 index = GPIO_CFG_INDEX(bank_offset);
32 u32 offset = GPIO_CFG_OFFSET(bank_offset);
33 u32 cfg;
34
35 cfg = readl(&pio->cfg[0] + index);
36 cfg >>= offset;
37
38 return cfg & 0xf;
39}
40
41int sunxi_gpio_get_cfgpin(u32 pin)
42{
43 u32 bank = GPIO_BANK(pin);
44 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
45
46 return sunxi_gpio_get_cfgbank(pio, pin);
47}
48
49int sunxi_gpio_set_drv(u32 pin, u32 val)
50{
51 u32 bank = GPIO_BANK(pin);
52 u32 index = GPIO_DRV_INDEX(pin);
53 u32 offset = GPIO_DRV_OFFSET(pin);
54 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
55
56 clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
57
58 return 0;
59}
60
61int sunxi_gpio_set_pull(u32 pin, u32 val)
62{
63 u32 bank = GPIO_BANK(pin);
64 u32 index = GPIO_PULL_INDEX(pin);
65 u32 offset = GPIO_PULL_OFFSET(pin);
66 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
67
68 clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
69
70 return 0;
71}
72
