1/* 2 * Sunxi A31 Power Management Unit register definition. 3 * 4 * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> 5 * http://linux-sunxi.org 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Berg Xing <bergxing@allwinnertech.com> 8 * Tom Cubie <tangliang@allwinnertech.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13#ifndef _SUNXI_PRCM_H 14#define _SUNXI_PRCM_H 15 16#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4) 17#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3) 18#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1) 19#define PRCM_CPUS_CFG_PRE_DIV(n) \ 20 __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n)) 21#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8) 22#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f) 23#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1) 24#define PRCM_CPUS_CFG_POST_DIV(n) \ 25 __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n)) 26#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16) 27#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3) 28#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0 29#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1 30#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2 31#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3 32#define PRCM_CPUS_CFG_CLK_SRC_LOSC \ 33 __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC) 34#define PRCM_CPUS_CFG_CLK_SRC_HOSC \ 35 __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC) 36#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \ 37 __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6) 38#define PRCM_CPUS_CFG_CLK_SRC_PDIV \ 39 __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV) 40 41#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0) 42#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3) 43#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1) 44#define PRCM_APB0_RATIO_DIV(n) \ 45 __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n)) 46 47#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0) 48#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1) 49 50#define PRCM_APB0_GATE_PIO (0x1 << 0) 51#define PRCM_APB0_GATE_IR (0x1 << 1) 52#define PRCM_APB0_GATE_TIMER01 (0x1 << 2) 53#define PRCM_APB0_GATE_P2WI (0x1 << 3) /* sun6i */ 54#define PRCM_APB0_GATE_RSB (0x1 << 3) /* sun8i */ 55#define PRCM_APB0_GATE_UART (0x1 << 4) 56#define PRCM_APB0_GATE_1WIRE (0x1 << 5) 57#define PRCM_APB0_GATE_I2C (0x1 << 6) 58 59#define PRCM_APB0_RESET_PIO (0x1 << 0) 60#define PRCM_APB0_RESET_IR (0x1 << 1) 61#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) 62#define PRCM_APB0_RESET_P2WI (0x1 << 3) 63#define PRCM_APB0_RESET_UART (0x1 << 4) 64#define PRCM_APB0_RESET_1WIRE (0x1 << 5) 65#define PRCM_APB0_RESET_I2C (0x1 << 6) 66 67#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0) 68#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1) 69#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4) 70#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \ 71 __PRCM_PLL_CTRL_USB_CLK_SRC(0x3) 72#define __PRCM_PLL_CTRL_USB_CLK_0 0x0 73#define __PRCM_PLL_CTRL_USB_CLK_1 0x1 74#define __PRCM_PLL_CTRL_USB_CLK_2 0x2 75#define __PRCM_PLL_CTRL_USB_CLK_3 0x3 76#define PRCM_PLL_CTRL_USB_CLK_0 \ 77 __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0) 78#define PRCM_PLL_CTRL_USB_CLK_1 \ 79 __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1) 80#define PRCM_PLL_CTRL_USB_CLK_2 \ 81 __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2) 82#define PRCM_PLL_CTRL_USB_CLK_3 \ 83 __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3) 84#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12) 85#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \ 86 __PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3) 87#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \ 88 __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) 89#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20) 90#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \ 91 __PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3) 92#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0 93#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1 94#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2 95#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3 96#define PRCM_PLL_CTRL_HOSC_CLK_0 \ 97 __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0) 98#define PRCM_PLL_CTRL_HOSC_CLK_1 \ 99 __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1) 100#define PRCM_PLL_CTRL_HOSC_CLK_2 \ 101 __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2) 102#define PRCM_PLL_CTRL_HOSC_CLK_3 \ 103 __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3) 104#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24) 105#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0) 106#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1) 107#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2) 108#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3) 109#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */ 110#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16) 111#define PRCM_PLL_CTRL_LDO_OUT_MASK \ 112 __PRCM_PLL_CTRL_LDO_OUT(0x7) 113/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */ 114#define PRCM_PLL_CTRL_LDO_OUT_L(n) \ 115 __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7) 116#define PRCM_PLL_CTRL_LDO_OUT_H(n) \ 117 __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7) 118#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \ 119 __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000) 120#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \ 121 __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160) 122#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24) 123#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24) 124 125#define PRCM_CLK_1WIRE_GATE (0x1 << 31) 126 127#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0) 128#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf) 129#define __PRCM_CLK_MOD0_M_X(n) (n - 1) 130#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n)) 131#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8) 132#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7) 133#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16) 134#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3) 135#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1) 136#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n)) 137#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20) 138#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7) 139#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24) 140#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7) 141#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31) 142 143#define PRCM_APB0_RESET_PIO (0x1 << 0) 144#define PRCM_APB0_RESET_IR (0x1 << 1) 145#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) 146#define PRCM_APB0_RESET_P2WI (0x1 << 3) 147#define PRCM_APB0_RESET_UART (0x1 << 4) 148#define PRCM_APB0_RESET_1WIRE (0x1 << 5) 149#define PRCM_APB0_RESET_I2C (0x1 << 6) 150 151#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8) 152#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7) 153#define __PRCM_CLK_OUTD_M_X() ((n) - 1) 154#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n)) 155#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20) 156#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7) 157#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1) 158#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n) 159#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24) 160#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3) 161#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0 162#define __PRCM_CLK_OUTD_SRC_LOSC 0x1 163#define __PRCM_CLK_OUTD_SRC_HOSC 0x2 164#define __PRCM_CLK_OUTD_SRC_ERR 0x3 165#define PRCM_CLK_OUTD_SRC_LOSC2 \ 166#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2) 167#define PRCM_CLK_OUTD_SRC_LOSC \ 168#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC) 169#define PRCM_CLK_OUTD_SRC_HOSC \ 170#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC) 171#define PRCM_CLK_OUTD_SRC_ERR \ 172#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR) 173#define PRCM_CLK_OUTD_EN (0x1 << 31) 174 175#define PRCM_CPU0_PWROFF (0x1 << 0) 176#define PRCM_CPU1_PWROFF (0x1 << 1) 177#define PRCM_CPU2_PWROFF (0x1 << 2) 178#define PRCM_CPU3_PWROFF (0x1 << 3) 179#define PRCM_CPU_ALL_PWROFF (0xf << 0) 180 181#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0) 182#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1) 183#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2) 184#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3) 185 186#define PRCM_VDD_GPU_PWROFF (0x1 << 0) 187 188#define PRCM_VDD_SYS_RESET (0x1 << 0) 189 190#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0) 191#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff) 192 193#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0) 194#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff) 195 196#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0) 197#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff) 198 199#ifndef __ASSEMBLY__ 200struct sunxi_prcm_reg { 201 u32 cpus_cfg; /* 0x000 */ 202 u8 res0[0x8]; /* 0x004 */ 203 u32 apb0_ratio; /* 0x00c */ 204 u32 cpu0_cfg; /* 0x010 */ 205 u32 cpu1_cfg; /* 0x014 */ 206 u32 cpu2_cfg; /* 0x018 */ 207 u32 cpu3_cfg; /* 0x01c */ 208 u8 res1[0x8]; /* 0x020 */ 209 u32 apb0_gate; /* 0x028 */ 210 u8 res2[0x14]; /* 0x02c */ 211 u32 pll_ctrl0; /* 0x040 */ 212 u32 pll_ctrl1; /* 0x044 */ 213 u8 res3[0x8]; /* 0x048 */ 214 u32 clk_1wire; /* 0x050 */ 215 u32 clk_ir; /* 0x054 */ 216 u8 res4[0x58]; /* 0x058 */ 217 u32 apb0_reset; /* 0x0b0 */ 218 u8 res5[0x3c]; /* 0x0b4 */ 219 u32 clk_outd; /* 0x0f0 */ 220 u8 res6[0xc]; /* 0x0f4 */ 221 u32 cpu_pwroff; /* 0x100 */ 222 u8 res7[0xc]; /* 0x104 */ 223 u32 vdd_sys_pwroff; /* 0x110 */ 224 u8 res8[0x4]; /* 0x114 */ 225 u32 gpu_pwroff; /* 0x118 */ 226 u8 res9[0x4]; /* 0x11c */ 227 u32 vdd_pwr_reset; /* 0x120 */ 228 u8 res10[0x20]; /* 0x124 */ 229 u32 cpu1_pwr_clamp; /* 0x144 */ 230 u32 cpu2_pwr_clamp; /* 0x148 */ 231 u32 cpu3_pwr_clamp; /* 0x14c */ 232 u8 res11[0x30]; /* 0x150 */ 233 u32 dram_pwr; /* 0x180 */ 234 u8 res12[0xc]; /* 0x184 */ 235 u32 dram_tst; /* 0x190 */ 236}; 237 238void prcm_apb0_enable(u32 flags); 239#endif /* __ASSEMBLY__ */ 240#endif /* _PRCM_H */ 241