1/* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef _ASM_CACHE_H 10#define _ASM_CACHE_H 11 12#include <asm/system.h> 13 14#ifndef CONFIG_ARM64 15 16/* 17 * Invalidate L2 Cache using co-proc instruction 18 */ 19static inline void invalidate_l2_cache(void) 20{ 21 unsigned int val=0; 22 23 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" 24 : : "r" (val) : "cc"); 25 isb(); 26} 27 28void l2_cache_enable(void); 29void l2_cache_disable(void); 30void set_section_dcache(int section, enum dcache_option option); 31 32void arm_init_before_mmu(void); 33void arm_init_domains(void); 34void cpu_cache_initialization(void); 35void dram_bank_mmu_setup(int bank); 36 37#endif 38 39/* 40 * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We 41 * use that value for aligning DMA buffers unless the board config has specified 42 * an alternate cache line size. 43 */ 44#ifdef CONFIG_SYS_CACHELINE_SIZE 45#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 46#else 47#define ARCH_DMA_MINALIGN 64 48#endif 49 50#endif /* _ASM_CACHE_H */ 51