LXR uboot/arch/arm/mach-uniphier/ph1-sld8/ddrphy

   1/*
   2 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <config.h>
   8#include <linux/types.h>
   9#include <linux/io.h>
  10#include <mach/ddrphy-regs.h>
  11
  12void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
  13{
  14        u32 tmp;
  15
  16        writel(0x0300c473, &phy->pgcr[1]);
  17        if (freq == 1333) {
  18                writel(0x0a806844, &phy->ptr[0]);
  19                writel(0x208e0124, &phy->ptr[1]);
  20        } else {
  21                writel(0x0c807d04, &phy->ptr[0]);
  22                writel(0x2710015E, &phy->ptr[1]);
  23        }
  24        writel(0x00083DEF, &phy->ptr[2]);
  25        if (freq == 1333) {
  26                writel(0x0f051616, &phy->ptr[3]);
  27                writel(0x06ae08d6, &phy->ptr[4]);
  28        } else {
  29                writel(0x12061A80, &phy->ptr[3]);
  30                writel(0x08027100, &phy->ptr[4]);
  31        }
  32        writel(0xF004001A, &phy->dsgcr);
  33
  34        /* change the value of the on-die pull-up/pull-down registors */
  35        tmp = readl(&phy->dxccr);
  36        tmp &= ~0x0ee0;
  37        tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
  38        writel(tmp, &phy->dxccr);
  39
  40        writel(0x0000040B, &phy->dcr);
  41        if (freq == 1333) {
  42                writel(0x85589955, &phy->dtpr[0]);
  43                if (size == 1)
  44                        writel(0x1a8363c0, &phy->dtpr[1]);
  45                else
  46                        writel(0x1a8363c0, &phy->dtpr[1]);
  47                writel(0x5002c200, &phy->dtpr[2]);
  48                writel(0x00000b51, &phy->mr0);
  49        } else {
  50                writel(0x999cbb66, &phy->dtpr[0]);
  51                if (size == 1)
  52                        writel(0x1a878400, &phy->dtpr[1]);
  53                else
  54                        writel(0x1a878400, &phy->dtpr[1]);
  55                writel(0xa00214f8, &phy->dtpr[2]);
  56                writel(0x00000d71, &phy->mr0);
  57        }
  58        writel(0x00000006, &phy->mr1);
  59        if (freq == 1333)
  60                writel(0x00000290, &phy->mr2);
  61        else
  62                writel(0x00000298, &phy->mr2);
  63
  64#ifdef CONFIG_DDR_STANDARD
  65        writel(0x00000000, &phy->mr3);
  66#else
  67        writel(0x00000800, &phy->mr3);
  68#endif
  69
  70        while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
  71                ;
  72
  73        writel(0x0300C473, &phy->pgcr[1]);
  74        writel(0x0000005D, &phy->zq[0].cr[1]);
  75}
  76