1/* 2 * (C) Copyright 2006 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * (C) Copyright 2006 6 * DAVE Srl <www.dave-tech.it> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11#ifndef _SDRAM_H_ 12#define _SDRAM_H_ 13 14#include <config.h> 15 16#define ONE_BILLION 1000000000 17 18struct sdram_conf_s { 19 unsigned long size; 20 int rows; 21 unsigned long reg; 22}; 23 24typedef struct sdram_conf_s sdram_conf_t; 25 26/* Bitfields offsets */ 27#define SDRAM0_TR_CASL (31 - 8) 28#define SDRAM0_TR_PTA (31 - 13) 29#define SDRAM0_TR_CTP (31 - 15) 30#define SDRAM0_TR_LDF (31 - 17) 31#define SDRAM0_TR_RFTA (31 - 29) 32#define SDRAM0_TR_RCD (31 - 31) 33 34#ifdef CONFIG_SYS_SDRAM_CL 35/* SDRAM timings [ns] according to AMCC/IBM names (see SDRAM_faq.doc) */ 36#define CONFIG_SYS_SDRAM_CASL CONFIG_SYS_SDRAM_CL 37#define CONFIG_SYS_SDRAM_PTA CONFIG_SYS_SDRAM_tRP 38#define CONFIG_SYS_SDRAM_CTP (CONFIG_SYS_SDRAM_tRC - CONFIG_SYS_SDRAM_tRCD - CONFIG_SYS_SDRAM_tRP) 39#define CONFIG_SYS_SDRAM_LDF 0 40#ifdef CONFIG_SYS_SDRAM_tRFC 41#define CONFIG_SYS_SDRAM_RFTA CONFIG_SYS_SDRAM_tRFC 42#else 43#define CONFIG_SYS_SDRAM_RFTA CONFIG_SYS_SDRAM_tRC 44#endif 45#define CONFIG_SYS_SDRAM_RCD CONFIG_SYS_SDRAM_tRCD 46#endif /* #ifdef CONFIG_SYS_SDRAM_CL */ 47 48/* 49 * Some defines for the 440 DDR controller 50 */ 51#define SDRAM_CFG0_DC_EN 0x80000000 /* SDRAM Controller Enable */ 52#define SDRAM_CFG0_MEMCHK 0x30000000 /* Memory data error checking mask*/ 53#define SDRAM_CFG0_MEMCHK_NON 0x00000000 /* No ECC generation */ 54#define SDRAM_CFG0_MEMCHK_GEN 0x20000000 /* ECC generation */ 55#define SDRAM_CFG0_MEMCHK_CHK 0x30000000 /* ECC generation and checking */ 56#define SDRAM_CFG0_DRAMWDTH 0x02000000 /* DRAM width mask */ 57#define SDRAM_CFG0_DRAMWDTH_32 0x00000000 /* 32 bits */ 58#define SDRAM_CFG0_DRAMWDTH_64 0x02000000 /* 64 bits */ 59 60#endif 61