LXR uboot/arch/powerpc/include/asm/global

   1/*
   2 * (C) Copyright 2002-2010
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef __ASM_GBL_DATA_H
   9#define __ASM_GBL_DATA_H
  10
  11#include "config.h"
  12#include "asm/types.h"
  13
  14/* Architecture-specific global data */
  15struct arch_global_data {
  16#if defined(CONFIG_FSL_ESDHC)
  17        u32 sdhc_clk;
  18#if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT)
  19        u8 sdhc_adapter;
  20#endif
  21#endif
  22#if defined(CONFIG_8xx)
  23        unsigned long brg_clk;
  24#endif
  25#if defined(CONFIG_CPM2)
  26        /* There are many clocks on the MPC8260 - see page 9-5 */
  27        unsigned long vco_out;
  28        unsigned long cpm_clk;
  29        unsigned long scc_clk;
  30        unsigned long brg_clk;
  31#endif
  32        /* TODO: sjg@chromium.org: Should these be unslgned long? */
  33#if defined(CONFIG_MPC83xx)
  34        /* There are other clocks in the MPC83XX */
  35        u32 csb_clk;
  36# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
  37        defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
  38        u32 tsec1_clk;
  39        u32 tsec2_clk;
  40        u32 usbdr_clk;
  41# elif defined(CONFIG_MPC8309)
  42        u32 usbdr_clk;
  43# endif
  44# if defined(CONFIG_MPC834x)
  45        u32 usbmph_clk;
  46# endif /* CONFIG_MPC834x */
  47# if defined(CONFIG_MPC8315)
  48        u32 tdm_clk;
  49# endif
  50        u32 core_clk;
  51        u32 enc_clk;
  52        u32 lbiu_clk;
  53        u32 lclk_clk;
  54# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
  55        defined(CONFIG_MPC837x)
  56        u32 pciexp1_clk;
  57        u32 pciexp2_clk;
  58# endif
  59# if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
  60        u32 sata_clk;
  61# endif
  62# if defined(CONFIG_MPC8360)
  63        u32 mem_sec_clk;
  64# endif /* CONFIG_MPC8360 */
  65#endif
  66#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
  67        u32 lbc_clk;
  68        void *cpu;
  69#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
  70#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
  71                defined(CONFIG_MPC86xx)
  72        u32 i2c1_clk;
  73        u32 i2c2_clk;
  74#endif
  75#if defined(CONFIG_QE)
  76        u32 qe_clk;
  77        u32 brg_clk;
  78        uint mp_alloc_base;
  79        uint mp_alloc_top;
  80#endif /* CONFIG_QE */
  81#if defined(CONFIG_FSL_LAW)
  82        u32 used_laws;
  83#endif
  84#if defined(CONFIG_E500)
  85        u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
  86#endif
  87#if defined(CONFIG_MPC5xxx)
  88        unsigned long ipb_clk;
  89#endif
  90#if defined(CONFIG_MPC512X)
  91        u32 ips_clk;
  92        u32 csb_clk;
  93#endif /* CONFIG_MPC512X */
  94        unsigned long reset_status;     /* reset status register at boot */
  95#if defined(CONFIG_MPC83xx)
  96        unsigned long arbiter_event_attributes;
  97        unsigned long arbiter_event_address;
  98#endif
  99#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
 100        unsigned int dp_alloc_base;
 101        unsigned int dp_alloc_top;
 102#endif
 103#if defined(CONFIG_4xx)
 104        u32 uart_clk;
 105#endif /* CONFIG_4xx */
 106#ifdef CONFIG_SYS_FPGA_COUNT
 107        unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
 108#endif
 109#if defined(CONFIG_WD_MAX_RATE)
 110        unsigned long long wdt_last;    /* trace watch-dog triggering rate */
 111#endif
 112#if defined(CONFIG_LWMON5)
 113        unsigned long kbd_status;
 114#endif
 115};
 116
 117#include <asm-generic/global_data.h>
 118
 119#if 1
 120#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r2")
 121#else /* We could use plain global data, but the resulting code is bigger */
 122#define XTRN_DECLARE_GLOBAL_DATA_PTR    extern
 123#define DECLARE_GLOBAL_DATA_PTR     XTRN_DECLARE_GLOBAL_DATA_PTR \
 124                                    gd_t *gd
 125#endif
 126
 127#endif /* __ASM_GBL_DATA_H */
 128