LXR uboot/board/olimex/mx23_olinuxino/spl

   1/*
   2 * Olimex MX23 Olinuxino Boot setup
   3 *
   4 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#include <common.h>
  10#include <config.h>
  11#include <asm/io.h>
  12#include <asm/arch/iomux-mx23.h>
  13#include <asm/arch/imx-regs.h>
  14#include <asm/arch/sys_proto.h>
  15
  16#define MUX_CONFIG_EMI  (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
  17#define MUX_CONFIG_SSP  (MXS_PAD_8MA | MXS_PAD_PULLUP)
  18
  19const iomux_cfg_t iomux_setup[] = {
  20        /* DUART */
  21        MX23_PAD_PWM0__DUART_RX,
  22        MX23_PAD_PWM1__DUART_TX,
  23
  24        /* EMI */
  25        MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
  26        MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
  27        MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
  28        MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
  29        MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
  30        MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
  31        MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
  32        MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
  33        MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
  34        MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
  35        MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
  36        MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
  37        MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
  38        MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
  39        MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
  40        MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
  41        MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
  42        MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
  43        MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
  44        MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
  45        MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
  46        MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
  47
  48        MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
  49        MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
  50        MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
  51        MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
  52        MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
  53        MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
  54        MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
  55        MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
  56        MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
  57        MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
  58        MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
  59        MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
  60        MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
  61        MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
  62        MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
  63
  64        MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
  65        MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
  66        MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
  67        MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
  68        MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
  69        MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
  70
  71        /* Green LED */
  72        MX23_PAD_SSP1_DETECT__GPIO_2_1 |
  73                (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL),
  74
  75        /* MMC 0 */
  76        MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
  77        MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
  78        MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
  79        MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
  80        MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
  81        MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
  82
  83        /* Ethernet */
  84        MX23_PAD_GPMI_ALE__GPIO_0_17 |
  85                (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
  86};
  87
  88void board_init_ll(const uint32_t arg, const uint32_t *resptr)
  89{
  90        mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
  91}
  92
  93/* Fine-tune the DRAM configuration. */
  94void mxs_adjust_memory_params(uint32_t *dram_vals)
  95{
  96        /* Enable Auto Precharge. */
  97        dram_vals[3] |= 1 << 8;
  98        /* Enable Fast Writes. */
  99        dram_vals[5] |= 1 << 8;
 100        /* tEMRS = 3*tCK */
 101        dram_vals[10] &= ~(0x3 << 8);
 102        dram_vals[10] |= (0x3 << 8);
 103        /* CASLAT = 3*tCK */
 104        dram_vals[11] &= ~(0x3 << 0);
 105        dram_vals[11] |= (0x3 << 0);
 106        /* tCKE = 1*tCK */
 107        dram_vals[12] &= ~(0x7 << 0);
 108        dram_vals[12] |= (0x1 << 0);
 109        /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
 110        dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
 111        dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
 112        /* tDAL = 6*tCK */
 113        dram_vals[15] &= ~(0xf << 16);
 114        dram_vals[15] |= (0x6 << 16);
 115        /* tREF = 1040*tCK */
 116        dram_vals[26] &= ~0xffff;
 117        dram_vals[26] |= 0x0410;
 118        /* tRAS_MAX = 9334*tCK */
 119        dram_vals[32] &= ~0xffff;
 120        dram_vals[32] |= 0x2475;
 121}
 122