LXR uboot/drivers/net/davinci

   1/*
   2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
   3 *
   4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   5 *
   6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
   7 * follows:
   8 *
   9 * ----------------------------------------------------------------------------
  10 *
  11 * dm644x_emac.c
  12 *
  13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
  14 *
  15 * Copyright (C) 2005 Texas Instruments.
  16 *
  17 * ----------------------------------------------------------------------------
  18 *
  19 * SPDX-License-Identifier:     GPL-2.0+
  20 *
  21 * Modifications:
  22 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
  23 * ver  1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
  24 */
  25#include <common.h>
  26#include <command.h>
  27#include <net.h>
  28#include <miiphy.h>
  29#include <malloc.h>
  30#include <netdev.h>
  31#include <linux/compiler.h>
  32#include <asm/arch/emac_defs.h>
  33#include <asm/io.h>
  34#include "davinci_emac.h"
  35
  36unsigned int    emac_dbg = 0;
  37#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
  38
  39#ifdef EMAC_HW_RAM_ADDR
  40static inline unsigned long BD_TO_HW(unsigned long x)
  41{
  42        if (x == 0)
  43                return 0;
  44
  45        return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
  46}
  47
  48static inline unsigned long HW_TO_BD(unsigned long x)
  49{
  50        if (x == 0)
  51                return 0;
  52
  53        return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR;
  54}
  55#else
  56#define BD_TO_HW(x)     (x)
  57#define HW_TO_BD(x)     (x)
  58#endif
  59
  60#ifdef DAVINCI_EMAC_GIG_ENABLE
  61#define emac_gigabit_enable(phy_addr)   davinci_eth_gigabit_enable(phy_addr)
  62#else
  63#define emac_gigabit_enable(phy_addr)   /* no gigabit to enable */
  64#endif
  65
  66#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
  67#define CONFIG_SYS_EMAC_TI_CLKDIV       ((EMAC_MDIO_BUS_FREQ / \
  68                EMAC_MDIO_CLOCK_FREQ) - 1)
  69#endif
  70
  71static void davinci_eth_mdio_enable(void);
  72
  73static int gen_init_phy(int phy_addr);
  74static int gen_is_phy_connected(int phy_addr);
  75static int gen_get_link_speed(int phy_addr);
  76static int gen_auto_negotiate(int phy_addr);
  77
  78void eth_mdio_enable(void)
  79{
  80        davinci_eth_mdio_enable();
  81}
  82
  83/* EMAC Addresses */
  84static volatile emac_regs       *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
  85static volatile ewrap_regs      *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
  86static volatile mdio_regs       *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
  87
  88/* EMAC descriptors */
  89static volatile emac_desc       *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
  90static volatile emac_desc       *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
  91static volatile emac_desc       *emac_rx_active_head = 0;
  92static volatile emac_desc       *emac_rx_active_tail = 0;
  93static int                      emac_rx_queue_active = 0;
  94
  95/* Receive packet buffers */
  96static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
  97                                __aligned(ARCH_DMA_MINALIGN);
  98
  99#ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
 100#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT       3
 101#endif
 102
 103/* PHY address for a discovered PHY (0xff - not found) */
 104static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
 105
 106/* number of PHY found active */
 107static u_int8_t num_phy;
 108
 109phy_t                           phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
 110
 111static inline void davinci_flush_rx_descs(void)
 112{
 113        /* flush the whole RX descs area */
 114        flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
 115                        EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
 116}
 117
 118static inline void davinci_invalidate_rx_descs(void)
 119{
 120        /* invalidate the whole RX descs area */
 121        invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
 122                        EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
 123}
 124
 125static inline void davinci_flush_desc(emac_desc *desc)
 126{
 127        flush_dcache_range((unsigned long)desc,
 128                        (unsigned long)desc + sizeof(*desc));
 129}
 130
 131static int davinci_eth_set_mac_addr(struct eth_device *dev)
 132{
 133        unsigned long           mac_hi;
 134        unsigned long           mac_lo;
 135
 136        /*
 137         * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
 138         * receive)
 139         *  Using channel 0 only - other channels are disabled
 140         *  */
 141        writel(0, &adap_emac->MACINDEX);
 142        mac_hi = (dev->enetaddr[3] << 24) |
 143                 (dev->enetaddr[2] << 16) |
 144                 (dev->enetaddr[1] << 8)  |
 145                 (dev->enetaddr[0]);
 146        mac_lo = (dev->enetaddr[5] << 8) |
 147                 (dev->enetaddr[4]);
 148
 149        writel(mac_hi, &adap_emac->MACADDRHI);
 150#if defined(DAVINCI_EMAC_VERSION2)
 151        writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
 152               &adap_emac->MACADDRLO);
 153#else
 154        writel(mac_lo, &adap_emac->MACADDRLO);
 155#endif
 156
 157        writel(0, &adap_emac->MACHASH1);
 158        writel(0, &adap_emac->MACHASH2);
 159
 160        /* Set source MAC address - REQUIRED */
 161        writel(mac_hi, &adap_emac->MACSRCADDRHI);
 162        writel(mac_lo, &adap_emac->MACSRCADDRLO);
 163
 164
 165        return 0;
 166}
 167
 168static void davinci_eth_mdio_enable(void)
 169{
 170        u_int32_t       clkdiv;
 171
 172        clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 173
 174        writel((clkdiv & 0xff) |
 175               MDIO_CONTROL_ENABLE |
 176               MDIO_CONTROL_FAULT |
 177               MDIO_CONTROL_FAULT_ENABLE,
 178               &adap_mdio->CONTROL);
 179
 180        while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
 181                ;
 182}
 183
 184/*
 185 * Tries to find an active connected PHY. Returns 1 if address if found.
 186 * If no active PHY (or more than one PHY) found returns 0.
 187 * Sets active_phy_addr variable.
 188 */
 189static int davinci_eth_phy_detect(void)
 190{
 191        u_int32_t       phy_act_state;
 192        int             i;
 193        int             j;
 194        unsigned int    count = 0;
 195
 196        for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
 197                active_phy_addr[i] = 0xff;
 198
 199        udelay(1000);
 200        phy_act_state = readl(&adap_mdio->ALIVE);
 201
 202        if (phy_act_state == 0)
 203                return 0;               /* No active PHYs */
 204
 205        debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
 206
 207        for (i = 0, j = 0; i < 32; i++)
 208                if (phy_act_state & (1 << i)) {
 209                        count++;
 210                        if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
 211                                active_phy_addr[j++] = i;
 212                        } else {
 213                                printf("%s: to many PHYs detected.\n",
 214                                        __func__);
 215                                count = 0;
 216                                break;
 217                        }
 218                }
 219
 220        num_phy = count;
 221
 222        return count;
 223}
 224
 225
 226/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
 227int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
 228{
 229        int     tmp;
 230
 231        while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
 232                ;
 233
 234        writel(MDIO_USERACCESS0_GO |
 235               MDIO_USERACCESS0_WRITE_READ |
 236               ((reg_num & 0x1f) << 21) |
 237               ((phy_addr & 0x1f) << 16),
 238               &adap_mdio->USERACCESS0);
 239
 240        /* Wait for command to complete */
 241        while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
 242                ;
 243
 244        if (tmp & MDIO_USERACCESS0_ACK) {
 245                *data = tmp & 0xffff;
 246                return(1);
 247        }
 248
 249        *data = -1;
 250        return(0);
 251}
 252
 253/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
 254int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
 255{
 256
 257        while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
 258                ;
 259
 260        writel(MDIO_USERACCESS0_GO |
 261               MDIO_USERACCESS0_WRITE_WRITE |
 262               ((reg_num & 0x1f) << 21) |
 263               ((phy_addr & 0x1f) << 16) |
 264               (data & 0xffff),
 265               &adap_mdio->USERACCESS0);
 266
 267        /* Wait for command to complete */
 268        while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
 269                ;
 270
 271        return(1);
 272}
 273
 274/* PHY functions for a generic PHY */
 275static int gen_init_phy(int phy_addr)
 276{
 277        int     ret = 1;
 278
 279        if (gen_get_link_speed(phy_addr)) {
 280                /* Try another time */
 281                ret = gen_get_link_speed(phy_addr);
 282        }
 283
 284        return(ret);
 285}
 286
 287static int gen_is_phy_connected(int phy_addr)
 288{
 289        u_int16_t       dummy;
 290
 291        return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
 292}
 293
 294static int get_active_phy(void)
 295{
 296        int i;
 297
 298        for (i = 0; i < num_phy; i++)
 299                if (phy[i].get_link_speed(active_phy_addr[i]))
 300                        return i;
 301
 302        return -1;      /* Return error if no link */
 303}
 304
 305static int gen_get_link_speed(int phy_addr)
 306{
 307        u_int16_t       tmp;
 308
 309        if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
 310                        (tmp & 0x04)) {
 311#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 312                defined(CONFIG_MACH_DAVINCI_DA850_EVM)
 313                davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
 314
 315                /* Speed doesn't matter, there is no setting for it in EMAC. */
 316                if (tmp & (LPA_100FULL | LPA_10FULL)) {
 317                        /* set EMAC for Full Duplex  */
 318                        writel(EMAC_MACCONTROL_MIIEN_ENABLE |
 319                                        EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
 320                                        &adap_emac->MACCONTROL);
 321                } else {
 322                        /*set EMAC for Half Duplex  */
 323                        writel(EMAC_MACCONTROL_MIIEN_ENABLE,
 324                                        &adap_emac->MACCONTROL);
 325                }
 326
 327                if (tmp & (LPA_100FULL | LPA_100HALF))
 328                        writel(readl(&adap_emac->MACCONTROL) |
 329                                        EMAC_MACCONTROL_RMIISPEED_100,
 330                                         &adap_emac->MACCONTROL);
 331                else
 332                        writel(readl(&adap_emac->MACCONTROL) &
 333                                        ~EMAC_MACCONTROL_RMIISPEED_100,
 334                                         &adap_emac->MACCONTROL);
 335#endif
 336                return(1);
 337        }
 338
 339        return(0);
 340}
 341
 342static int gen_auto_negotiate(int phy_addr)
 343{
 344        u_int16_t       tmp;
 345        u_int16_t       val;
 346        unsigned long   cntr = 0;
 347
 348        if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
 349                return 0;
 350
 351        val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
 352                                                BMCR_SPEED100;
 353        davinci_eth_phy_write(phy_addr, MII_BMCR, val);
 354
 355        if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
 356                return 0;
 357
 358        val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
 359                                                        ADVERTISE_10HALF);
 360        davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
 361
 362        if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
 363                return(0);
 364
 365        /* Restart Auto_negotiation  */
 366        tmp |= BMCR_ANRESTART;
 367        davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
 368
 369        /*check AutoNegotiate complete */
 370        do {
 371                udelay(40000);
 372                if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
 373                        return 0;
 374
 375                if (tmp & BMSR_ANEGCOMPLETE)
 376                        break;
 377
 378                cntr++;
 379        } while (cntr < 200);
 380
 381        if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
 382                return(0);
 383
 384        if (!(tmp & BMSR_ANEGCOMPLETE))
 385                return(0);
 386
 387        return(gen_get_link_speed(phy_addr));
 388}
 389/* End of generic PHY functions */
 390
 391
 392#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 393static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
 394{
 395        return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1);
 396}
 397
 398static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value)
 399{
 400        return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
 401}
 402#endif
 403
 404static void  __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
 405{
 406        u_int16_t data;
 407
 408        if (davinci_eth_phy_read(phy_addr, 0, &data)) {
 409                if (data & (1 << 6)) { /* speed selection MSB */
 410                        /*
 411                         * Check if link detected is giga-bit
 412                         * If Gigabit mode detected, enable gigbit in MAC
 413                         */
 414                        writel(readl(&adap_emac->MACCONTROL) |
 415                                EMAC_MACCONTROL_GIGFORCE |
 416                                EMAC_MACCONTROL_GIGABIT_ENABLE,
 417                                &adap_emac->MACCONTROL);
 418                }
 419        }
 420}
 421
 422/* Eth device open */
 423static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
 424{
 425        dv_reg_p                addr;
 426        u_int32_t               clkdiv, cnt;
 427        volatile emac_desc      *rx_desc;
 428        int                     index;
 429
 430        debug_emac("+ emac_open\n");
 431
 432        /* Reset EMAC module and disable interrupts in wrapper */
 433        writel(1, &adap_emac->SOFTRESET);
 434        while (readl(&adap_emac->SOFTRESET) != 0)
 435                ;
 436#if defined(DAVINCI_EMAC_VERSION2)
 437        writel(1, &adap_ewrap->softrst);
 438        while (readl(&adap_ewrap->softrst) != 0)
 439                ;
 440#else
 441        writel(0, &adap_ewrap->EWCTL);
 442        for (cnt = 0; cnt < 5; cnt++) {
 443                clkdiv = readl(&adap_ewrap->EWCTL);
 444        }
 445#endif
 446
 447#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 448        defined(CONFIG_MACH_DAVINCI_DA850_EVM)
 449        adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
 450        adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
 451        adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
 452#endif
 453        rx_desc = emac_rx_desc;
 454
 455        writel(1, &adap_emac->TXCONTROL);
 456        writel(1, &adap_emac->RXCONTROL);
 457
 458        davinci_eth_set_mac_addr(dev);
 459
 460        /* Set DMA 8 TX / 8 RX Head pointers to 0 */
 461        addr = &adap_emac->TX0HDP;
 462        for(cnt = 0; cnt < 16; cnt++)
 463                writel(0, addr++);
 464
 465        addr = &adap_emac->RX0HDP;
 466        for(cnt = 0; cnt < 16; cnt++)
 467                writel(0, addr++);
 468
 469        /* Clear Statistics (do this before setting MacControl register) */
 470        addr = &adap_emac->RXGOODFRAMES;
 471        for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
 472                writel(0, addr++);
 473
 474        /* No multicast addressing */
 475        writel(0, &adap_emac->MACHASH1);
 476        writel(0, &adap_emac->MACHASH2);
 477
 478        /* Create RX queue and set receive process in place */
 479        emac_rx_active_head = emac_rx_desc;
 480        for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
 481                rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
 482                rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
 483                rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
 484                rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
 485                rx_desc++;
 486        }
 487
 488        /* Finalize the rx desc list */
 489        rx_desc--;
 490        rx_desc->next = 0;
 491        emac_rx_active_tail = rx_desc;
 492        emac_rx_queue_active = 1;
 493
 494        davinci_flush_rx_descs();
 495
 496        /* Enable TX/RX */
 497        writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
 498        writel(0, &adap_emac->RXBUFFEROFFSET);
 499
 500        /*
 501         * No fancy configs - Use this for promiscous debug
 502         *   - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
 503         */
 504        writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
 505
 506        /* Enable ch 0 only */
 507        writel(1, &adap_emac->RXUNICASTSET);
 508
 509        /* Enable MII interface and Full duplex mode */
 510#if defined(CONFIG_SOC_DA8XX) || \
 511        (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
 512        writel((EMAC_MACCONTROL_MIIEN_ENABLE |
 513                EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
 514                EMAC_MACCONTROL_RMIISPEED_100),
 515               &adap_emac->MACCONTROL);
 516#else
 517        writel((EMAC_MACCONTROL_MIIEN_ENABLE |
 518                EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
 519               &adap_emac->MACCONTROL);
 520#endif
 521
 522        /* Init MDIO & get link state */
 523        clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 524        writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
 525               &adap_mdio->CONTROL);
 526
 527        /* We need to wait for MDIO to start */
 528        udelay(1000);
 529
 530        index = get_active_phy();
 531        if (index == -1)
 532                return(0);
 533
 534        emac_gigabit_enable(active_phy_addr[index]);
 535
 536        /* Start receive process */
 537        writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);
 538
 539        debug_emac("- emac_open\n");
 540
 541        return(1);
 542}
 543
 544/* EMAC Channel Teardown */
 545static void davinci_eth_ch_teardown(int ch)
 546{
 547        dv_reg          dly = 0xff;
 548        dv_reg          cnt;
 549
 550        debug_emac("+ emac_ch_teardown\n");
 551
 552        if (ch == EMAC_CH_TX) {
 553                /* Init TX channel teardown */
 554                writel(0, &adap_emac->TXTEARDOWN);
 555                do {
 556                        /*
 557                         * Wait here for Tx teardown completion interrupt to
 558                         * occur. Note: A task delay can be called here to pend
 559                         * rather than occupying CPU cycles - anyway it has
 560                         * been found that teardown takes very few cpu cycles
 561                         * and does not affect functionality
 562                         */
 563                        dly--;
 564                        udelay(1);
 565                        if (dly == 0)
 566                                break;
 567                        cnt = readl(&adap_emac->TX0CP);
 568                } while (cnt != 0xfffffffc);
 569                writel(cnt, &adap_emac->TX0CP);
 570                writel(0, &adap_emac->TX0HDP);
 571        } else {
 572                /* Init RX channel teardown */
 573                writel(0, &adap_emac->RXTEARDOWN);
 574                do {
 575                        /*
 576                         * Wait here for Rx teardown completion interrupt to
 577                         * occur. Note: A task delay can be called here to pend
 578                         * rather than occupying CPU cycles - anyway it has
 579                         * been found that teardown takes very few cpu cycles
 580                         * and does not affect functionality
 581                         */
 582                        dly--;
 583                        udelay(1);
 584                        if (dly == 0)
 585                                break;
 586                        cnt = readl(&adap_emac->RX0CP);
 587                } while (cnt != 0xfffffffc);
 588                writel(cnt, &adap_emac->RX0CP);
 589                writel(0, &adap_emac->RX0HDP);
 590        }
 591
 592        debug_emac("- emac_ch_teardown\n");
 593}
 594
 595/* Eth device close */
 596static void davinci_eth_close(struct eth_device *dev)
 597{
 598        debug_emac("+ emac_close\n");
 599
 600        davinci_eth_ch_teardown(EMAC_CH_TX);    /* TX Channel teardown */
 601        davinci_eth_ch_teardown(EMAC_CH_RX);    /* RX Channel teardown */
 602
 603        /* Reset EMAC module and disable interrupts in wrapper */
 604        writel(1, &adap_emac->SOFTRESET);
 605#if defined(DAVINCI_EMAC_VERSION2)
 606        writel(1, &adap_ewrap->softrst);
 607#else
 608        writel(0, &adap_ewrap->EWCTL);
 609#endif
 610
 611#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 612        defined(CONFIG_MACH_DAVINCI_DA850_EVM)
 613        adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
 614        adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
 615        adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
 616#endif
 617        debug_emac("- emac_close\n");
 618}
 619
 620static int tx_send_loop = 0;
 621
 622/*
 623 * This function sends a single packet on the network and returns
 624 * positive number (number of bytes transmitted) or negative for error
 625 */
 626static int davinci_eth_send_packet (struct eth_device *dev,
 627                                        void *packet, int length)
 628{
 629        int ret_status = -1;
 630        int index;
 631        tx_send_loop = 0;
 632
 633        index = get_active_phy();
 634        if (index == -1) {
 635                printf(" WARN: emac_send_packet: No link\n");
 636                return (ret_status);
 637        }
 638
 639        emac_gigabit_enable(active_phy_addr[index]);
 640
 641        /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
 642        if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
 643                length = EMAC_MIN_ETHERNET_PKT_SIZE;
 644        }
 645
 646        /* Populate the TX descriptor */
 647        emac_tx_desc->next = 0;
 648        emac_tx_desc->buffer = (u_int8_t *) packet;
 649        emac_tx_desc->buff_off_len = (length & 0xffff);
 650        emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
 651                                      EMAC_CPPI_SOP_BIT |
 652                                      EMAC_CPPI_OWNERSHIP_BIT |
 653                                      EMAC_CPPI_EOP_BIT);
 654
 655        flush_dcache_range((unsigned long)packet,
 656                        (unsigned long)packet + length);
 657        davinci_flush_desc(emac_tx_desc);
 658
 659        /* Send the packet */
 660        writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
 661
 662        /* Wait for packet to complete or link down */
 663        while (1) {
 664                if (!phy[index].get_link_speed(active_phy_addr[index])) {
 665                        davinci_eth_ch_teardown (EMAC_CH_TX);
 666                        return (ret_status);
 667                }
 668
 669                emac_gigabit_enable(active_phy_addr[index]);
 670
 671                if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
 672                        ret_status = length;
 673                        break;
 674                }
 675                tx_send_loop++;
 676        }
 677
 678        return (ret_status);
 679}
 680
 681/*
 682 * This function handles receipt of a packet from the network
 683 */
 684static int davinci_eth_rcv_packet (struct eth_device *dev)
 685{
 686        volatile emac_desc *rx_curr_desc;
 687        volatile emac_desc *curr_desc;
 688        volatile emac_desc *tail_desc;
 689        int status, ret = -1;
 690
 691        davinci_invalidate_rx_descs();
 692
 693        rx_curr_desc = emac_rx_active_head;
 694        status = rx_curr_desc->pkt_flag_len;
 695        if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
 696                if (status & EMAC_CPPI_RX_ERROR_FRAME) {
 697                        /* Error in packet - discard it and requeue desc */
 698                        printf ("WARN: emac_rcv_pkt: Error in packet\n");
 699                } else {
 700                        unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
 701
 702                        invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE);
 703                        net_process_received_packet(
 704                                rx_curr_desc->buffer,
 705                                rx_curr_desc->buff_off_len & 0xffff);
 706                        ret = rx_curr_desc->buff_off_len & 0xffff;
 707                }
 708
 709                /* Ack received packet descriptor */
 710                writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);
 711                curr_desc = rx_curr_desc;
 712                emac_rx_active_head =
 713                        (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
 714
 715                if (status & EMAC_CPPI_EOQ_BIT) {
 716                        if (emac_rx_active_head) {
 717                                writel(BD_TO_HW((ulong)emac_rx_active_head),
 718                                       &adap_emac->RX0HDP);
 719                        } else {
 720                                emac_rx_queue_active = 0;
 721                                printf ("INFO:emac_rcv_packet: RX Queue not active\n");
 722                        }
 723                }
 724
 725                /* Recycle RX descriptor */
 726                rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
 727                rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
 728                rx_curr_desc->next = 0;
 729                davinci_flush_desc(rx_curr_desc);
 730
 731                if (emac_rx_active_head == 0) {
 732                        printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
 733                        emac_rx_active_head = curr_desc;
 734                        emac_rx_active_tail = curr_desc;
 735                        if (emac_rx_queue_active != 0) {
 736                                writel(BD_TO_HW((ulong)emac_rx_active_head),
 737                                       &adap_emac->RX0HDP);
 738                                printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
 739                                emac_rx_queue_active = 1;
 740                        }
 741                } else {
 742                        tail_desc = emac_rx_active_tail;
 743                        emac_rx_active_tail = curr_desc;
 744                        tail_desc->next = BD_TO_HW((ulong) curr_desc);
 745                        status = tail_desc->pkt_flag_len;
 746                        if (status & EMAC_CPPI_EOQ_BIT) {
 747                                davinci_flush_desc(tail_desc);
 748                                writel(BD_TO_HW((ulong)curr_desc),
 749                                       &adap_emac->RX0HDP);
 750                                status &= ~EMAC_CPPI_EOQ_BIT;
 751                                tail_desc->pkt_flag_len = status;
 752                        }
 753                        davinci_flush_desc(tail_desc);
 754                }
 755                return (ret);
 756        }
 757        return (0);
 758}
 759
 760/*
 761 * This function initializes the emac hardware. It does NOT initialize
 762 * EMAC modules power or pin multiplexors, that is done by board_init()
 763 * much earlier in bootup process. Returns 1 on success, 0 otherwise.
 764 */
 765int davinci_emac_initialize(void)
 766{
 767        u_int32_t       phy_id;
 768        u_int16_t       tmp;
 769        int             i;
 770        int             ret;
 771        struct eth_device *dev;
 772
 773        dev = malloc(sizeof *dev);
 774
 775        if (dev == NULL)
 776                return -1;
 777
 778        memset(dev, 0, sizeof *dev);
 779        sprintf(dev->name, "DaVinci-EMAC");
 780
 781        dev->iobase = 0;
 782        dev->init = davinci_eth_open;
 783        dev->halt = davinci_eth_close;
 784        dev->send = davinci_eth_send_packet;
 785        dev->recv = davinci_eth_rcv_packet;
 786        dev->write_hwaddr = davinci_eth_set_mac_addr;
 787
 788        eth_register(dev);
 789
 790        davinci_eth_mdio_enable();
 791
 792        /* let the EMAC detect the PHYs */
 793        udelay(5000);
 794
 795        for (i = 0; i < 256; i++) {
 796                if (readl(&adap_mdio->ALIVE))
 797                        break;
 798                udelay(1000);
 799        }
 800
 801        if (i >= 256) {
 802                printf("No ETH PHY detected!!!\n");
 803                return(0);
 804        }
 805
 806        /* Find if PHY(s) is/are connected */
 807        ret = davinci_eth_phy_detect();
 808        if (!ret)
 809                return(0);
 810        else
 811                debug_emac(" %d ETH PHY detected\n", ret);
 812
 813        /* Get PHY ID and initialize phy_ops for a detected PHY */
 814        for (i = 0; i < num_phy; i++) {
 815                if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
 816                                                        &tmp)) {
 817                        active_phy_addr[i] = 0xff;
 818                        continue;
 819                }
 820
 821                phy_id = (tmp << 16) & 0xffff0000;
 822
 823                if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
 824                                                        &tmp)) {
 825                        active_phy_addr[i] = 0xff;
 826                        continue;
 827                }
 828
 829                phy_id |= tmp & 0x0000ffff;
 830
 831                switch (phy_id) {
 832#ifdef PHY_KSZ8873
 833                case PHY_KSZ8873:
 834                        sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
 835                                                active_phy_addr[i]);
 836                        phy[i].init = ksz8873_init_phy;
 837                        phy[i].is_phy_connected = ksz8873_is_phy_connected;
 838                        phy[i].get_link_speed = ksz8873_get_link_speed;
 839                        phy[i].auto_negotiate = ksz8873_auto_negotiate;
 840                        break;
 841#endif
 842#ifdef PHY_LXT972
 843                case PHY_LXT972:
 844                        sprintf(phy[i].name, "LXT972 @ 0x%02x",
 845                                                active_phy_addr[i]);
 846                        phy[i].init = lxt972_init_phy;
 847                        phy[i].is_phy_connected = lxt972_is_phy_connected;
 848                        phy[i].get_link_speed = lxt972_get_link_speed;
 849                        phy[i].auto_negotiate = lxt972_auto_negotiate;
 850                        break;
 851#endif
 852#ifdef PHY_DP83848
 853                case PHY_DP83848:
 854                        sprintf(phy[i].name, "DP83848 @ 0x%02x",
 855                                                active_phy_addr[i]);
 856                        phy[i].init = dp83848_init_phy;
 857                        phy[i].is_phy_connected = dp83848_is_phy_connected;
 858                        phy[i].get_link_speed = dp83848_get_link_speed;
 859                        phy[i].auto_negotiate = dp83848_auto_negotiate;
 860                        break;
 861#endif
 862#ifdef PHY_ET1011C
 863                case PHY_ET1011C:
 864                        sprintf(phy[i].name, "ET1011C @ 0x%02x",
 865                                                active_phy_addr[i]);
 866                        phy[i].init = gen_init_phy;
 867                        phy[i].is_phy_connected = gen_is_phy_connected;
 868                        phy[i].get_link_speed = et1011c_get_link_speed;
 869                        phy[i].auto_negotiate = gen_auto_negotiate;
 870                        break;
 871#endif
 872                default:
 873                        sprintf(phy[i].name, "GENERIC @ 0x%02x",
 874                                                active_phy_addr[i]);
 875                        phy[i].init = gen_init_phy;
 876                        phy[i].is_phy_connected = gen_is_phy_connected;
 877                        phy[i].get_link_speed = gen_get_link_speed;
 878                        phy[i].auto_negotiate = gen_auto_negotiate;
 879                }
 880
 881                debug("Ethernet PHY: %s\n", phy[i].name);
 882
 883                miiphy_register(phy[i].name, davinci_mii_phy_read,
 884                                                davinci_mii_phy_write);
 885        }
 886
 887#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 888                defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
 889                        !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
 890        for (i = 0; i < num_phy; i++) {
 891                if (phy[i].is_phy_connected(i))
 892                        phy[i].auto_negotiate(i);
 893        }
 894#endif
 895        return(1);
 896}
 897