LXR uboot/drivers/spi/mxs

   1/*
   2 * Freescale i.MX28 SPI driver
   3 *
   4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5 * on behalf of DENX Software Engineering GmbH
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 *
   9 * NOTE: This driver only supports the SPI-controller chipselects,
  10 *       GPIO driven chipselects are not supported.
  11 */
  12
  13#include <common.h>
  14#include <malloc.h>
  15#include <spi.h>
  16#include <asm/errno.h>
  17#include <asm/io.h>
  18#include <asm/arch/clock.h>
  19#include <asm/arch/imx-regs.h>
  20#include <asm/arch/sys_proto.h>
  21#include <asm/imx-common/dma.h>
  22
  23#define MXS_SPI_MAX_TIMEOUT     1000000
  24#define MXS_SPI_PORT_OFFSET     0x2000
  25#define MXS_SSP_CHIPSELECT_MASK         0x00300000
  26#define MXS_SSP_CHIPSELECT_SHIFT        20
  27
  28#define MXSSSP_SMALL_TRANSFER   512
  29
  30struct mxs_spi_slave {
  31        struct spi_slave        slave;
  32        uint32_t                max_khz;
  33        uint32_t                mode;
  34        struct mxs_ssp_regs     *regs;
  35};
  36
  37static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
  38{
  39        return container_of(slave, struct mxs_spi_slave, slave);
  40}
  41
  42void spi_init(void)
  43{
  44}
  45
  46int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  47{
  48        /* MXS SPI: 4 ports and 3 chip selects maximum */
  49        if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
  50                return 0;
  51        else
  52                return 1;
  53}
  54
  55struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  56                                  unsigned int max_hz, unsigned int mode)
  57{
  58        struct mxs_spi_slave *mxs_slave;
  59
  60        if (!spi_cs_is_valid(bus, cs)) {
  61                printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
  62                return NULL;
  63        }
  64
  65        mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
  66        if (!mxs_slave)
  67                return NULL;
  68
  69        if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
  70                goto err_init;
  71
  72        mxs_slave->max_khz = max_hz / 1000;
  73        mxs_slave->mode = mode;
  74        mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
  75
  76        return &mxs_slave->slave;
  77
  78err_init:
  79        free(mxs_slave);
  80        return NULL;
  81}
  82
  83void spi_free_slave(struct spi_slave *slave)
  84{
  85        struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
  86        free(mxs_slave);
  87}
  88
  89int spi_claim_bus(struct spi_slave *slave)
  90{
  91        struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
  92        struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
  93        uint32_t reg = 0;
  94
  95        mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
  96
  97        writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
  98               SSP_CTRL0_BUS_WIDTH_ONE_BIT,
  99               &ssp_regs->hw_ssp_ctrl0);
 100
 101        reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
 102        reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
 103        reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
 104        writel(reg, &ssp_regs->hw_ssp_ctrl1);
 105
 106        writel(0, &ssp_regs->hw_ssp_cmd0);
 107
 108        mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
 109
 110        return 0;
 111}
 112
 113void spi_release_bus(struct spi_slave *slave)
 114{
 115}
 116
 117static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
 118{
 119        writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
 120        writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
 121}
 122
 123static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
 124{
 125        writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
 126        writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
 127}
 128
 129static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
 130                        char *data, int length, int write, unsigned long flags)
 131{
 132        struct mxs_ssp_regs *ssp_regs = slave->regs;
 133
 134        if (flags & SPI_XFER_BEGIN)
 135                mxs_spi_start_xfer(ssp_regs);
 136
 137        while (length--) {
 138                /* We transfer 1 byte */
 139#if defined(CONFIG_MX23)
 140                writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
 141                writel(1, &ssp_regs->hw_ssp_ctrl0_set);
 142#elif defined(CONFIG_MX28)
 143                writel(1, &ssp_regs->hw_ssp_xfer_size);
 144#endif
 145
 146                if ((flags & SPI_XFER_END) && !length)
 147                        mxs_spi_end_xfer(ssp_regs);
 148
 149                if (write)
 150                        writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
 151                else
 152                        writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
 153
 154                writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
 155
 156                if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
 157                        SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
 158                        printf("MXS SPI: Timeout waiting for start\n");
 159                        return -ETIMEDOUT;
 160                }
 161
 162                if (write)
 163                        writel(*data++, &ssp_regs->hw_ssp_data);
 164
 165                writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
 166
 167                if (!write) {
 168                        if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
 169                                SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
 170                                printf("MXS SPI: Timeout waiting for data\n");
 171                                return -ETIMEDOUT;
 172                        }
 173
 174                        *data = readl(&ssp_regs->hw_ssp_data);
 175                        data++;
 176                }
 177
 178                if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
 179                        SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
 180                        printf("MXS SPI: Timeout waiting for finish\n");
 181                        return -ETIMEDOUT;
 182                }
 183        }
 184
 185        return 0;
 186}
 187
 188static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 189                        char *data, int length, int write, unsigned long flags)
 190{
 191        const int xfer_max_sz = 0xff00;
 192        const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
 193        struct mxs_ssp_regs *ssp_regs = slave->regs;
 194        struct mxs_dma_desc *dp;
 195        uint32_t ctrl0;
 196        uint32_t cache_data_count;
 197        const uint32_t dstart = (uint32_t)data;
 198        int dmach;
 199        int tl;
 200        int ret = 0;
 201
 202#if defined(CONFIG_MX23)
 203        const int mxs_spi_pio_words = 1;
 204#elif defined(CONFIG_MX28)
 205        const int mxs_spi_pio_words = 4;
 206#endif
 207
 208        ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
 209
 210        memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
 211
 212        ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
 213        ctrl0 |= SSP_CTRL0_DATA_XFER;
 214
 215        if (flags & SPI_XFER_BEGIN)
 216                ctrl0 |= SSP_CTRL0_LOCK_CS;
 217        if (!write)
 218                ctrl0 |= SSP_CTRL0_READ;
 219
 220        if (length % ARCH_DMA_MINALIGN)
 221                cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
 222        else
 223                cache_data_count = length;
 224
 225        /* Flush data to DRAM so DMA can pick them up */
 226        if (write)
 227                flush_dcache_range(dstart, dstart + cache_data_count);
 228
 229        /* Invalidate the area, so no writeback into the RAM races with DMA */
 230        invalidate_dcache_range(dstart, dstart + cache_data_count);
 231
 232        dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
 233
 234        dp = desc;
 235        while (length) {
 236                dp->address = (dma_addr_t)dp;
 237                dp->cmd.address = (dma_addr_t)data;
 238
 239                /*
 240                 * This is correct, even though it does indeed look insane.
 241                 * I hereby have to, wholeheartedly, thank Freescale Inc.,
 242                 * for always inventing insane hardware and keeping me busy
 243                 * and employed ;-)
 244                 */
 245                if (write)
 246                        dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
 247                else
 248                        dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
 249
 250                /*
 251                 * The DMA controller can transfer large chunks (64kB) at
 252                 * time by setting the transfer length to 0. Setting tl to
 253                 * 0x10000 will overflow below and make .data contain 0.
 254                 * Otherwise, 0xff00 is the transfer maximum.
 255                 */
 256                if (length >= 0x10000)
 257                        tl = 0x10000;
 258                else
 259                        tl = min(length, xfer_max_sz);
 260
 261                dp->cmd.data |=
 262                        ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
 263                        (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
 264                        MXS_DMA_DESC_HALT_ON_TERMINATE |
 265                        MXS_DMA_DESC_TERMINATE_FLUSH;
 266
 267                data += tl;
 268                length -= tl;
 269
 270                if (!length) {
 271                        dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
 272
 273                        if (flags & SPI_XFER_END) {
 274                                ctrl0 &= ~SSP_CTRL0_LOCK_CS;
 275                                ctrl0 |= SSP_CTRL0_IGNORE_CRC;
 276                        }
 277                }
 278
 279                /*
 280                 * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
 281                 * case of MX28, write only CTRL0 in case of MX23 due
 282                 * to the difference in register layout. It is utterly
 283                 * essential that the XFER_SIZE register is written on
 284                 * a per-descriptor basis with the same size as is the
 285                 * descriptor!
 286                 */
 287                dp->cmd.pio_words[0] = ctrl0;
 288#ifdef CONFIG_MX28
 289                dp->cmd.pio_words[1] = 0;
 290                dp->cmd.pio_words[2] = 0;
 291                dp->cmd.pio_words[3] = tl;
 292#endif
 293
 294                mxs_dma_desc_append(dmach, dp);
 295
 296                dp++;
 297        }
 298
 299        if (mxs_dma_go(dmach))
 300                ret = -EINVAL;
 301
 302        /* The data arrived into DRAM, invalidate cache over them */
 303        if (!write)
 304                invalidate_dcache_range(dstart, dstart + cache_data_count);
 305
 306        return ret;
 307}
 308
 309int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 310                const void *dout, void *din, unsigned long flags)
 311{
 312        struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
 313        struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
 314        int len = bitlen / 8;
 315        char dummy;
 316        int write = 0;
 317        char *data = NULL;
 318        int dma = 1;
 319
 320        if (bitlen == 0) {
 321                if (flags & SPI_XFER_END) {
 322                        din = (void *)&dummy;
 323                        len = 1;
 324                } else
 325                        return 0;
 326        }
 327
 328        /* Half-duplex only */
 329        if (din && dout)
 330                return -EINVAL;
 331        /* No data */
 332        if (!din && !dout)
 333                return 0;
 334
 335        if (dout) {
 336                data = (char *)dout;
 337                write = 1;
 338        } else if (din) {
 339                data = (char *)din;
 340                write = 0;
 341        }
 342
 343        /*
 344         * Check for alignment, if the buffer is aligned, do DMA transfer,
 345         * PIO otherwise. This is a temporary workaround until proper bounce
 346         * buffer is in place.
 347         */
 348        if (dma) {
 349                if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
 350                        dma = 0;
 351                if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
 352                        dma = 0;
 353        }
 354
 355        if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
 356                writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
 357                return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
 358        } else {
 359                writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
 360                return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
 361        }
 362}
 363