1
2
3
4
5
6
7
8
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_T4240QDS
14#define CONFIG_PHYS_64BIT
15
16#define CONFIG_FSL_SATA_V2
17#define CONFIG_PCIE4
18#define CONFIG_FSL_CAAM
19
20#define CONFIG_ICS307_REFCLK_HZ 25000000
21
22#ifdef CONFIG_RAMBOOT_PBL
23#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
24#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
25#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
26#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
28#else
29#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
30#define CONFIG_SPL_ENV_SUPPORT
31#define CONFIG_SPL_SERIAL_SUPPORT
32#define CONFIG_SPL_FLUSH_IMAGE
33#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34#define CONFIG_SPL_LIBGENERIC_SUPPORT
35#define CONFIG_SPL_LIBCOMMON_SUPPORT
36#define CONFIG_SPL_I2C_SUPPORT
37#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
38#define CONFIG_FSL_LAW
39#define CONFIG_SYS_TEXT_BASE 0x00201000
40#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
41#define CONFIG_SPL_PAD_TO 0x40000
42#define CONFIG_SPL_MAX_SIZE 0x28000
43#define RESET_VECTOR_OFFSET 0x27FFC
44#define BOOT_PAGE_OFFSET 0x27000
45
46#ifdef CONFIG_NAND
47#define CONFIG_SPL_NAND_SUPPORT
48#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
49#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
50#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
51#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
52#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
53#define CONFIG_SPL_NAND_BOOT
54#endif
55
56#ifdef CONFIG_SDCARD
57#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
58#define CONFIG_SPL_MMC_SUPPORT
59#define CONFIG_SPL_MMC_MINIMAL
60#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
61#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
62#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
63#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
64#ifndef CONFIG_SPL_BUILD
65#define CONFIG_SYS_MPC85XX_NO_RESETVEC
66#endif
67#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
68#define CONFIG_SPL_MMC_BOOT
69#endif
70
71#ifdef CONFIG_SPL_BUILD
72#define CONFIG_SPL_SKIP_RELOCATE
73#define CONFIG_SPL_COMMON_INIT_DDR
74#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
75#define CONFIG_SYS_NO_FLASH
76#endif
77
78#endif
79#endif
80
81#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
82
83#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
84#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
85 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
86#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
87#define CONFIG_SYS_NO_FLASH
88#endif
89
90#define CONFIG_SRIO_PCIE_BOOT_MASTER
91#define CONFIG_DDR_ECC
92
93#include "t4qds.h"
94
95#ifdef CONFIG_SYS_NO_FLASH
96#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
97#define CONFIG_ENV_IS_NOWHERE
98#endif
99#else
100#define CONFIG_FLASH_CFI_DRIVER
101#define CONFIG_SYS_FLASH_CFI
102#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
103#endif
104
105#if defined(CONFIG_SPIFLASH)
106#define CONFIG_SYS_EXTRA_ENV_RELOC
107#define CONFIG_ENV_IS_IN_SPI_FLASH
108#define CONFIG_ENV_SPI_BUS 0
109#define CONFIG_ENV_SPI_CS 0
110#define CONFIG_ENV_SPI_MAX_HZ 10000000
111#define CONFIG_ENV_SPI_MODE 0
112#define CONFIG_ENV_SIZE 0x2000
113#define CONFIG_ENV_OFFSET 0x100000
114#define CONFIG_ENV_SECT_SIZE 0x10000
115#elif defined(CONFIG_SDCARD)
116#define CONFIG_SYS_EXTRA_ENV_RELOC
117#define CONFIG_ENV_IS_IN_MMC
118#define CONFIG_SYS_MMC_ENV_DEV 0
119#define CONFIG_ENV_SIZE 0x2000
120#define CONFIG_ENV_OFFSET (512 * 0x800)
121#elif defined(CONFIG_NAND)
122#define CONFIG_SYS_EXTRA_ENV_RELOC
123#define CONFIG_ENV_IS_IN_NAND
124#define CONFIG_ENV_SIZE 0x2000
125#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
126#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
127#define CONFIG_ENV_IS_IN_REMOTE
128#define CONFIG_ENV_ADDR 0xffe20000
129#define CONFIG_ENV_SIZE 0x2000
130#elif defined(CONFIG_ENV_IS_NOWHERE)
131#define CONFIG_ENV_SIZE 0x2000
132#else
133#define CONFIG_ENV_IS_IN_FLASH
134#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
135#define CONFIG_ENV_SIZE 0x2000
136#define CONFIG_ENV_SECT_SIZE 0x20000
137#endif
138
139#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
140#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
141
142#ifndef __ASSEMBLY__
143unsigned long get_board_sys_clk(void);
144unsigned long get_board_ddr_clk(void);
145#endif
146
147
148#define CONFIG_ID_EEPROM
149#define CONFIG_SYS_I2C_EEPROM_NXID
150#define CONFIG_SYS_EEPROM_BUS_NUM 0
151#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
152#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
153
154
155
156
157#define CONFIG_SYS_SPD_BUS_NUM 0
158#define SPD_EEPROM_ADDRESS1 0x51
159#define SPD_EEPROM_ADDRESS2 0x52
160#define SPD_EEPROM_ADDRESS3 0x53
161#define SPD_EEPROM_ADDRESS4 0x54
162#define SPD_EEPROM_ADDRESS5 0x55
163#define SPD_EEPROM_ADDRESS6 0x56
164#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
165#define CONFIG_SYS_SDRAM_SIZE 4096
166
167
168
169
170#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
171#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
172 + 0x8000000) | \
173 CSPR_PORT_SIZE_16 | \
174 CSPR_MSEL_NOR | \
175 CSPR_V)
176#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
177#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
178 CSPR_PORT_SIZE_16 | \
179 CSPR_MSEL_NOR | \
180 CSPR_V)
181#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
182
183#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
184
185#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
186 FTIM0_NOR_TEADC(0x5) | \
187 FTIM0_NOR_TEAHC(0x5))
188#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
189 FTIM1_NOR_TRAD_NOR(0x1A) |\
190 FTIM1_NOR_TSEQRAD_NOR(0x13))
191#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
192 FTIM2_NOR_TCH(0x4) | \
193 FTIM2_NOR_TWPH(0x0E) | \
194 FTIM2_NOR_TWP(0x1c))
195#define CONFIG_SYS_NOR_FTIM3 0x0
196
197#define CONFIG_SYS_FLASH_QUIET_TEST
198#define CONFIG_FLASH_SHOW_PROGRESS 45
199
200#define CONFIG_SYS_MAX_FLASH_BANKS 2
201#define CONFIG_SYS_MAX_FLASH_SECT 1024
202#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
203#define CONFIG_SYS_FLASH_WRITE_TOUT 500
204
205#define CONFIG_SYS_FLASH_EMPTY_INFO
206#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
207 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
208
209#define CONFIG_FSL_QIXIS
210#define QIXIS_BASE 0xffdf0000
211#define QIXIS_LBMAP_SWITCH 6
212#define QIXIS_LBMAP_MASK 0x0f
213#define QIXIS_LBMAP_SHIFT 0
214#define QIXIS_LBMAP_DFLTBANK 0x00
215#define QIXIS_LBMAP_ALTBANK 0x04
216#define QIXIS_RST_CTL_RESET 0x83
217#define QIXIS_RST_FORCE_MEM 0x1
218#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
219#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
220#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
221#define QIXIS_BRDCFG5 0x55
222#define QIXIS_MUX_SDHC 2
223#define QIXIS_MUX_SDHC_WIDTH8 1
224#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
225
226#define CONFIG_SYS_CSPR3_EXT (0xf)
227#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
228 | CSPR_PORT_SIZE_8 \
229 | CSPR_MSEL_GPCM \
230 | CSPR_V)
231#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
232#define CONFIG_SYS_CSOR3 0x0
233
234#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
235 FTIM0_GPCM_TEADC(0x0e) | \
236 FTIM0_GPCM_TEAHC(0x0e))
237#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
238 FTIM1_GPCM_TRAD(0x3f))
239#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
240 FTIM2_GPCM_TCH(0x8) | \
241 FTIM2_GPCM_TWP(0x1f))
242#define CONFIG_SYS_CS3_FTIM3 0x0
243
244
245#define CONFIG_NAND_FSL_IFC
246#define CONFIG_SYS_NAND_BASE 0xff800000
247#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
248
249#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
250#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
251 | CSPR_PORT_SIZE_8 \
252 | CSPR_MSEL_NAND \
253 | CSPR_V)
254#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
255
256#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
257 | CSOR_NAND_ECC_DEC_EN \
258 | CSOR_NAND_ECC_MODE_4 \
259 | CSOR_NAND_RAL_3 \
260 | CSOR_NAND_PGS_2K \
261 | CSOR_NAND_SPRZ_64 \
262 | CSOR_NAND_PB(64))
263
264#define CONFIG_SYS_NAND_ONFI_DETECTION
265
266
267#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
268 FTIM0_NAND_TWP(0x18) | \
269 FTIM0_NAND_TWCHT(0x07) | \
270 FTIM0_NAND_TWH(0x0a))
271#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
272 FTIM1_NAND_TWBE(0x39) | \
273 FTIM1_NAND_TRR(0x0e) | \
274 FTIM1_NAND_TRP(0x18))
275#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
276 FTIM2_NAND_TREH(0x0a) | \
277 FTIM2_NAND_TWHRE(0x1e))
278#define CONFIG_SYS_NAND_FTIM3 0x0
279
280#define CONFIG_SYS_NAND_DDR_LAW 11
281
282#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
283#define CONFIG_SYS_MAX_NAND_DEVICE 1
284#define CONFIG_CMD_NAND
285
286#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
287#define CONFIG_SYS_NAND_MAX_OOBFREE 2
288#define CONFIG_SYS_NAND_MAX_ECCPOS 256
289
290#if defined(CONFIG_NAND)
291#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
292#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
293#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
294#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
295#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
296#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
297#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
298#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
299#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
300#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
301#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
302#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
303#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
304#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
305#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
306#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
307#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
308#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
309#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
310#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
311#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
312#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
313#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
314#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
315#else
316#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
317#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
318#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
319#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
320#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
321#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
322#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
323#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
324#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
325#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
326#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
327#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
328#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
329#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
330#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
331#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
332#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
333#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
334#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
335#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
336#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
337#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
338#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
339#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
340#endif
341
342#if defined(CONFIG_RAMBOOT_PBL)
343#define CONFIG_SYS_RAMBOOT
344#endif
345
346
347
348#define CONFIG_SYS_FSL_I2C_SPEED 100000
349#define CONFIG_SYS_FSL_I2C2_SPEED 100000
350#define I2C_MUX_PCA_ADDR_PRI 0x77
351#define I2C_MUX_PCA_ADDR_SEC 0x76
352
353#define I2C_MUX_CH_DEFAULT 0x8
354#define I2C_MUX_CH_VOL_MONITOR 0xa
355#define I2C_MUX_CH_VSC3316_FS 0xc
356#define I2C_MUX_CH_VSC3316_BS 0xd
357
358
359#define I2C_VOL_MONITOR_ADDR 0x40
360#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
361#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
362#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
363
364
365#define CONFIG_VSC_CROSSBAR
366#define VSC3316_FSM_TX_ADDR 0x70
367#define VSC3316_FSM_RX_ADDR 0x71
368
369
370
371
372
373
374
375
376
377#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
378#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
379#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
380#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
381
382
383
384
385#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
386#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
387#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
388
389
390#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
391#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
392
393
394
395
396#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
397#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
398#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
399 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
400#endif
401
402
403
404#define CONFIG_FSL_ESPI
405#define CONFIG_SPI_FLASH_SST
406#define CONFIG_CMD_SF
407#define CONFIG_SF_DEFAULT_SPEED 10000000
408#define CONFIG_SF_DEFAULT_MODE 0
409
410
411
412#ifndef CONFIG_NOBQFMAN
413#define CONFIG_SYS_DPAA_QBMAN
414#define CONFIG_SYS_BMAN_NUM_PORTALS 50
415#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
416#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
417#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
418#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
419#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
420#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
421#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
422#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
423 CONFIG_SYS_BMAN_CENA_SIZE)
424#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
425#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
426#define CONFIG_SYS_QMAN_NUM_PORTALS 50
427#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
428#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
429#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
430#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
431#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
432#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
433#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
434#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
435 CONFIG_SYS_QMAN_CENA_SIZE)
436#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
437#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
438
439#define CONFIG_SYS_DPAA_FMAN
440#define CONFIG_SYS_DPAA_PME
441#define CONFIG_SYS_PMAN
442#define CONFIG_SYS_DPAA_DCE
443#define CONFIG_SYS_DPAA_RMAN
444#define CONFIG_SYS_INTERLAKEN
445
446
447#if defined(CONFIG_SPIFLASH)
448
449
450
451
452#define CONFIG_SYS_QE_FW_IN_SPIFLASH
453#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
454#elif defined(CONFIG_SDCARD)
455
456
457
458
459
460#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
461#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
462#elif defined(CONFIG_NAND)
463#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
464#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
465#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
466
467
468
469
470
471
472
473#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
474#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
475#else
476#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
477#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
478#endif
479#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
480#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
481#endif
482
483#ifdef CONFIG_SYS_DPAA_FMAN
484#define CONFIG_FMAN_ENET
485#define CONFIG_PHYLIB_10G
486#define CONFIG_PHY_VITESSE
487#define CONFIG_PHY_TERANETICS
488#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
489#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
490#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
491#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
492#define FM1_10GEC1_PHY_ADDR 0x0
493#define FM1_10GEC2_PHY_ADDR 0x1
494#define FM2_10GEC1_PHY_ADDR 0x2
495#define FM2_10GEC2_PHY_ADDR 0x3
496#endif
497
498
499
500#ifdef CONFIG_FSL_SATA_V2
501#define CONFIG_LIBATA
502#define CONFIG_FSL_SATA
503
504#define CONFIG_SYS_SATA_MAX_DEVICE 2
505#define CONFIG_SATA1
506#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
507#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
508#define CONFIG_SATA2
509#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
510#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
511
512#define CONFIG_LBA48
513#define CONFIG_CMD_SATA
514#define CONFIG_DOS_PARTITION
515#define CONFIG_CMD_EXT2
516#endif
517
518#ifdef CONFIG_FMAN_ENET
519#define CONFIG_MII
520#define CONFIG_ETHPRIME "FM1@DTSEC1"
521#define CONFIG_PHY_GIGE
522#endif
523
524
525#ifdef CONFIG_FSL_CAAM
526#define CONFIG_CMD_HASH
527#define CONFIG_SHA_HW_ACCEL
528#endif
529
530
531
532
533#define CONFIG_CMD_USB
534#define CONFIG_USB_STORAGE
535#define CONFIG_USB_EHCI
536#define CONFIG_USB_EHCI_FSL
537#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
538#define CONFIG_CMD_EXT2
539#define CONFIG_HAS_FSL_DR_USB
540
541#define CONFIG_MMC
542
543#ifdef CONFIG_MMC
544#define CONFIG_FSL_ESDHC
545#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
546#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
547#define CONFIG_CMD_MMC
548#define CONFIG_GENERIC_MMC
549#define CONFIG_CMD_EXT2
550#define CONFIG_CMD_FAT
551#define CONFIG_DOS_PARTITION
552#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
553#define CONFIG_ESDHC_DETECT_QUIRK \
554 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
555 IS_SVR_REV(get_svr(), 1, 0))
556#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
557 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
558#endif
559
560#define CONFIG_BOOTDELAY 10
561
562#define __USB_PHY_TYPE utmi
563
564
565
566
567
568
569
570#ifdef CONFIG_PPC_T4240
571#define CTRL_INTLV_PREFERED 3way_4KB
572#else
573#define CTRL_INTLV_PREFERED cacheline
574#endif
575
576#define CONFIG_EXTRA_ENV_SETTINGS \
577 "hwconfig=fsl_ddr:" \
578 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
579 "bank_intlv=auto;" \
580 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
581 "netdev=eth0\0" \
582 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
583 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
584 "tftpflash=tftpboot $loadaddr $uboot && " \
585 "protect off $ubootaddr +$filesize && " \
586 "erase $ubootaddr +$filesize && " \
587 "cp.b $loadaddr $ubootaddr $filesize && " \
588 "protect on $ubootaddr +$filesize && " \
589 "cmp.b $loadaddr $ubootaddr $filesize\0" \
590 "consoledev=ttyS0\0" \
591 "ramdiskaddr=2000000\0" \
592 "ramdiskfile=t4240qds/ramdisk.uboot\0" \
593 "fdtaddr=c00000\0" \
594 "fdtfile=t4240qds/t4240qds.dtb\0" \
595 "bdev=sda3\0"
596
597#define CONFIG_HVBOOT \
598 "setenv bootargs config-addr=0x60000000; " \
599 "bootm 0x01000000 - 0x00f00000"
600
601#define CONFIG_ALU \
602 "setenv bootargs root=/dev/$bdev rw " \
603 "console=$consoledev,$baudrate $othbootargs;" \
604 "cpu 1 release 0x01000000 - - -;" \
605 "cpu 2 release 0x01000000 - - -;" \
606 "cpu 3 release 0x01000000 - - -;" \
607 "cpu 4 release 0x01000000 - - -;" \
608 "cpu 5 release 0x01000000 - - -;" \
609 "cpu 6 release 0x01000000 - - -;" \
610 "cpu 7 release 0x01000000 - - -;" \
611 "go 0x01000000"
612
613#define CONFIG_LINUX \
614 "setenv bootargs root=/dev/ram rw " \
615 "console=$consoledev,$baudrate $othbootargs;" \
616 "setenv ramdiskaddr 0x02000000;" \
617 "setenv fdtaddr 0x00c00000;" \
618 "setenv loadaddr 0x1000000;" \
619 "bootm $loadaddr $ramdiskaddr $fdtaddr"
620
621#define CONFIG_HDBOOT \
622 "setenv bootargs root=/dev/$bdev rw " \
623 "console=$consoledev,$baudrate $othbootargs;" \
624 "tftp $loadaddr $bootfile;" \
625 "tftp $fdtaddr $fdtfile;" \
626 "bootm $loadaddr - $fdtaddr"
627
628#define CONFIG_NFSBOOTCOMMAND \
629 "setenv bootargs root=/dev/nfs rw " \
630 "nfsroot=$serverip:$rootpath " \
631 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
632 "console=$consoledev,$baudrate $othbootargs;" \
633 "tftp $loadaddr $bootfile;" \
634 "tftp $fdtaddr $fdtfile;" \
635 "bootm $loadaddr - $fdtaddr"
636
637#define CONFIG_RAMBOOTCOMMAND \
638 "setenv bootargs root=/dev/ram rw " \
639 "console=$consoledev,$baudrate $othbootargs;" \
640 "tftp $ramdiskaddr $ramdiskfile;" \
641 "tftp $loadaddr $bootfile;" \
642 "tftp $fdtaddr $fdtfile;" \
643 "bootm $loadaddr $ramdiskaddr $fdtaddr"
644
645#define CONFIG_BOOTCOMMAND CONFIG_LINUX
646
647#include <asm/fsl_secure_boot.h>
648
649#ifdef CONFIG_SECURE_BOOT
650#define CONFIG_CMD_BLOB
651#endif
652
653#endif
654
