1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 21#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ 22#define CONFIG_SYS_GENERIC_BOARD 23#define CONFIG_DISPLAY_BOARDINFO 24 25#define CONFIG_SYS_TEXT_BASE 0x40000000 26 27#ifdef CONFIG_LCD /* with LCD controller ? */ 28#define CONFIG_MPC8XX_LCD 29#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ 30#define CONFIG_LCD_INFO 1 /* ... and some board info */ 31#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ 32#endif 33 34#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 35#define CONFIG_SYS_SMC_RXBUFLEN 128 36#define CONFIG_SYS_MAXIDLE 10 37#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 38 39#define CONFIG_BOOTCOUNT_LIMIT 40 41#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 42 43#define CONFIG_BOARD_TYPES 1 /* support board types */ 44 45#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 46 47#undef CONFIG_BOOTARGS 48 49#define CONFIG_EXTRA_ENV_SETTINGS \ 50 "netdev=eth0\0" \ 51 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 52 "nfsroot=${serverip}:${rootpath}\0" \ 53 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 54 "addip=setenv bootargs ${bootargs} " \ 55 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 56 ":${hostname}:${netdev}:off panic=1\0" \ 57 "flash_nfs=run nfsargs addip;" \ 58 "bootm ${kernel_addr}\0" \ 59 "flash_self=run ramargs addip;" \ 60 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 61 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 62 "rootpath=/opt/eldk/ppc_8xx\0" \ 63 "hostname=TQM823L\0" \ 64 "bootfile=TQM823L/uImage\0" \ 65 "fdt_addr=40040000\0" \ 66 "kernel_addr=40060000\0" \ 67 "ramdisk_addr=40200000\0" \ 68 "u-boot=TQM823L/u-image.bin\0" \ 69 "load=tftp 200000 ${u-boot}\0" \ 70 "update=prot off 40000000 +${filesize};" \ 71 "era 40000000 +${filesize};" \ 72 "cp.b 200000 40000000 ${filesize};" \ 73 "sete filesize;save\0" \ 74 "" 75#define CONFIG_BOOTCOMMAND "run flash_self" 76 77#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 78#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 79 80#undef CONFIG_WATCHDOG /* watchdog disabled */ 81 82#if defined(CONFIG_LCD) 83# undef CONFIG_STATUS_LED /* disturbs display */ 84#else 85# define CONFIG_STATUS_LED 1 /* Status LED enabled */ 86#endif /* CONFIG_LCD */ 87 88#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 89 90/* 91 * BOOTP options 92 */ 93#define CONFIG_BOOTP_SUBNETMASK 94#define CONFIG_BOOTP_GATEWAY 95#define CONFIG_BOOTP_HOSTNAME 96#define CONFIG_BOOTP_BOOTPATH 97#define CONFIG_BOOTP_BOOTFILESIZE 98 99 100#define CONFIG_MAC_PARTITION 101#define CONFIG_DOS_PARTITION 102 103#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 104 105 106/* 107 * Command line configuration. 108 */ 109#define CONFIG_CMD_ASKENV 110#define CONFIG_CMD_DATE 111#define CONFIG_CMD_DHCP 112#define CONFIG_CMD_ELF 113#define CONFIG_CMD_EXT2 114#define CONFIG_CMD_IDE 115#define CONFIG_CMD_JFFS2 116#define CONFIG_CMD_SNTP 117 118#ifdef CONFIG_SPLASH_SCREEN 119 #define CONFIG_CMD_BMP 120#endif 121 122 123#define CONFIG_NETCONSOLE 124 125/* 126 * Miscellaneous configurable options 127 */ 128#define CONFIG_SYS_LONGHELP /* undef to save memory */ 129 130#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 131#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 132 133#if defined(CONFIG_CMD_KGDB) 134#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 135#else 136#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 137#endif 138#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 139#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 140#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 141 142#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 143#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 144 145#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 146 147/* 148 * Low Level Configuration Settings 149 * (address mappings, register initial values, etc.) 150 * You should know what you are doing if you make changes here. 151 */ 152/*----------------------------------------------------------------------- 153 * Internal Memory Mapped Register 154 */ 155#define CONFIG_SYS_IMMR 0xFFF00000 156 157/*----------------------------------------------------------------------- 158 * Definitions for initial stack pointer and data area (in DPRAM) 159 */ 160#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 161#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 162#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 163#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 164 165/*----------------------------------------------------------------------- 166 * Start addresses for the final memory configuration 167 * (Set up by the startup code) 168 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 169 */ 170#define CONFIG_SYS_SDRAM_BASE 0x00000000 171#define CONFIG_SYS_FLASH_BASE 0x40000000 172#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 173#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 174#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 175 176/* 177 * For booting Linux, the board info and command line data 178 * have to be in the first 8 MB of memory, since this is 179 * the maximum mapped by the Linux kernel during initialization. 180 */ 181#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 182 183/*----------------------------------------------------------------------- 184 * FLASH organization 185 */ 186 187/* use CFI flash driver */ 188#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 189#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 190#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 191#define CONFIG_SYS_FLASH_EMPTY_INFO 192#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 193#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 194#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 195 196#define CONFIG_ENV_IS_IN_FLASH 1 197#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 198#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 199 200/* Address and size of Redundant Environment Sector */ 201#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 202#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 203 204#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 205 206#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 207 208/*----------------------------------------------------------------------- 209 * Dynamic MTD partition support 210 */ 211#define CONFIG_CMD_MTDPARTS 212#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 213#define CONFIG_FLASH_CFI_MTD 214#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 215 216#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 217 "128k(dtb)," \ 218 "1664k(kernel)," \ 219 "2m(rootfs)," \ 220 "4m(data)" 221 222/*----------------------------------------------------------------------- 223 * Hardware Information Block 224 */ 225#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 226#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 227#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 228 229/*----------------------------------------------------------------------- 230 * Cache Configuration 231 */ 232#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 233#if defined(CONFIG_CMD_KGDB) 234#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 235#endif 236 237/*----------------------------------------------------------------------- 238 * SYPCR - System Protection Control 11-9 239 * SYPCR can only be written once after reset! 240 *----------------------------------------------------------------------- 241 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 242 */ 243#if defined(CONFIG_WATCHDOG) 244#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 245 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 246#else 247#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 248#endif 249 250/*----------------------------------------------------------------------- 251 * SIUMCR - SIU Module Configuration 11-6 252 *----------------------------------------------------------------------- 253 * PCMCIA config., multi-function pin tri-state 254 */ 255#ifndef CONFIG_CAN_DRIVER 256#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 257#else /* we must activate GPL5 in the SIUMCR for CAN */ 258#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 259#endif /* CONFIG_CAN_DRIVER */ 260 261/*----------------------------------------------------------------------- 262 * TBSCR - Time Base Status and Control 11-26 263 *----------------------------------------------------------------------- 264 * Clear Reference Interrupt Status, Timebase freezing enabled 265 */ 266#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 267 268/*----------------------------------------------------------------------- 269 * RTCSC - Real-Time Clock Status and Control Register 11-27 270 *----------------------------------------------------------------------- 271 */ 272#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 273 274/*----------------------------------------------------------------------- 275 * PISCR - Periodic Interrupt Status and Control 11-31 276 *----------------------------------------------------------------------- 277 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 278 */ 279#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 280 281/*----------------------------------------------------------------------- 282 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 283 *----------------------------------------------------------------------- 284 * Reset PLL lock status sticky bit, timer expired status bit and timer 285 * interrupt status bit 286 */ 287#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 288 289/*----------------------------------------------------------------------- 290 * SCCR - System Clock and reset Control Register 15-27 291 *----------------------------------------------------------------------- 292 * Set clock output, timebase and RTC source and divider, 293 * power management and some other internal clocks 294 */ 295#define SCCR_MASK SCCR_EBDF11 296#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 297 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 298 SCCR_DFALCD00) 299 300/*----------------------------------------------------------------------- 301 * PCMCIA stuff 302 *----------------------------------------------------------------------- 303 * 304 */ 305#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 306#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 307#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 308#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 309#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 310#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 311#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 312#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 313 314/*----------------------------------------------------------------------- 315 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 316 *----------------------------------------------------------------------- 317 */ 318 319#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 320#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 321 322#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 323#undef CONFIG_IDE_LED /* LED for ide not supported */ 324#undef CONFIG_IDE_RESET /* reset for ide not supported */ 325 326#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 327#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 328 329#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 330 331#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 332 333/* Offset for data I/O */ 334#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 335 336/* Offset for normal register accesses */ 337#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 338 339/* Offset for alternate registers */ 340#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 341 342/*----------------------------------------------------------------------- 343 * 344 *----------------------------------------------------------------------- 345 * 346 */ 347#define CONFIG_SYS_DER 0 348 349/* 350 * Init Memory Controller: 351 * 352 * BR0/1 and OR0/1 (FLASH) 353 */ 354 355#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 356#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 357 358/* used to re-map FLASH both when starting from SRAM or FLASH: 359 * restrict access enough to keep SRAM working (if any) 360 * but not too much to meddle with FLASH accesses 361 */ 362#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 363#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 364 365/* 366 * FLASH timing: 367 */ 368#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 369 OR_SCY_3_CLK | OR_EHTR | OR_BI) 370 371#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 372#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 373#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 374 375#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 376#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 377#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 378 379/* 380 * BR2/3 and OR2/3 (SDRAM) 381 * 382 */ 383#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 384#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 385#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 386 387/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 388#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 389 390#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 391#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 392 393#ifndef CONFIG_CAN_DRIVER 394#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 395#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 396#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 397#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 398#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 399#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 400#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 401 BR_PS_8 | BR_MS_UPMB | BR_V ) 402#endif /* CONFIG_CAN_DRIVER */ 403 404/* 405 * Memory Periodic Timer Prescaler 406 * 407 * The Divider for PTA (refresh timer) configuration is based on an 408 * example SDRAM configuration (64 MBit, one bank). The adjustment to 409 * the number of chip selects (NCS) and the actually needed refresh 410 * rate is done by setting MPTPR. 411 * 412 * PTA is calculated from 413 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 414 * 415 * gclk CPU clock (not bus clock!) 416 * Trefresh Refresh cycle * 4 (four word bursts used) 417 * 418 * 4096 Rows from SDRAM example configuration 419 * 1000 factor s -> ms 420 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 421 * 4 Number of refresh cycles per period 422 * 64 Refresh cycle in ms per number of rows 423 * -------------------------------------------- 424 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 425 * 426 * 50 MHz => 50.000.000 / Divider = 98 427 * 66 Mhz => 66.000.000 / Divider = 129 428 * 80 Mhz => 80.000.000 / Divider = 156 429 */ 430 431#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 432#define CONFIG_SYS_MAMR_PTA 98 433 434/* 435 * For 16 MBit, refresh rates could be 31.3 us 436 * (= 64 ms / 2K = 125 / quad bursts). 437 * For a simpler initialization, 15.6 us is used instead. 438 * 439 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 440 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 441 */ 442#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 443#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 444 445/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 446#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 447#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 448 449/* 450 * MAMR settings for SDRAM 451 */ 452 453/* 8 column SDRAM */ 454#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 455 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 456 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 457/* 9 column SDRAM */ 458#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 459 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 460 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 461 462/* pass open firmware flat tree */ 463#define CONFIG_OF_LIBFDT 1 464#define CONFIG_OF_BOARD_SETUP 1 465#define CONFIG_HWCONFIG 1 466 467#endif /* __CONFIG_H */ 468