1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC866 1 /* This is a MPC866 CPU */ 21#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ 22#define CONFIG_SYS_GENERIC_BOARD 23#define CONFIG_DISPLAY_BOARDINFO 24 25#define CONFIG_SYS_TEXT_BASE 0x40000000 26 27#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ 28#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ 29#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ 30#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ 31 /* (it will be used if there is no */ 32 /* 'cpuclk' variable with valid value) */ 33 34#undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */ 35 /* (function measure_gclk() */ 36 /* will be called) */ 37#ifdef CONFIG_SYS_MEASURE_CPUCLK 38#define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */ 39#endif 40 41#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 42#define CONFIG_SYS_SMC_RXBUFLEN 128 43#define CONFIG_SYS_MAXIDLE 10 44#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 45 46#define CONFIG_BOOTCOUNT_LIMIT 47 48#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 49 50#define CONFIG_BOARD_TYPES 1 /* support board types */ 51 52#define CONFIG_PREBOOT "echo;" \ 53 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 54 "echo" 55 56#undef CONFIG_BOOTARGS 57 58#define CONFIG_EXTRA_ENV_SETTINGS \ 59 "netdev=eth0\0" \ 60 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 61 "nfsroot=${serverip}:${rootpath}\0" \ 62 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 63 "addip=setenv bootargs ${bootargs} " \ 64 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 65 ":${hostname}:${netdev}:off panic=1\0" \ 66 "flash_nfs=run nfsargs addip;" \ 67 "bootm ${kernel_addr}\0" \ 68 "flash_self=run ramargs addip;" \ 69 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 70 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 71 "rootpath=/opt/eldk/ppc_8xx\0" \ 72 "hostname=TQM866M\0" \ 73 "bootfile=TQM866M/uImage\0" \ 74 "fdt_addr=400C0000\0" \ 75 "kernel_addr=40100000\0" \ 76 "ramdisk_addr=40280000\0" \ 77 "u-boot=TQM866M/u-image.bin\0" \ 78 "load=tftp 200000 ${u-boot}\0" \ 79 "update=prot off 40000000 +${filesize};" \ 80 "era 40000000 +${filesize};" \ 81 "cp.b 200000 40000000 ${filesize};" \ 82 "sete filesize;save\0" \ 83 "" 84#define CONFIG_BOOTCOMMAND "run flash_self" 85 86#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 87#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 88 89#undef CONFIG_WATCHDOG /* watchdog disabled */ 90 91#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 92 93#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 94 95/* enable I2C and select the hardware/software driver */ 96#define CONFIG_SYS_I2C 97#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 98#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ 99#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE 100 101/* 102 * Software (bit-bang) I2C driver configuration 103 */ 104#define PB_SCL 0x00000020 /* PB 26 */ 105#define PB_SDA 0x00000010 /* PB 27 */ 106 107#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 108#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 109#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 110#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 111#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 112 else immr->im_cpm.cp_pbdat &= ~PB_SDA 113#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 114 else immr->im_cpm.cp_pbdat &= ~PB_SCL 115#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ 116 117#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ 118#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ 119#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 120#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 121 122/* 123 * BOOTP options 124 */ 125#define CONFIG_BOOTP_SUBNETMASK 126#define CONFIG_BOOTP_GATEWAY 127#define CONFIG_BOOTP_HOSTNAME 128#define CONFIG_BOOTP_BOOTPATH 129#define CONFIG_BOOTP_BOOTFILESIZE 130 131 132#define CONFIG_MAC_PARTITION 133#define CONFIG_DOS_PARTITION 134 135#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ 136 137#define CONFIG_TIMESTAMP /* but print image timestmps */ 138 139 140/* 141 * Command line configuration. 142 */ 143#define CONFIG_CMD_ASKENV 144#define CONFIG_CMD_DHCP 145#define CONFIG_CMD_EEPROM 146#define CONFIG_CMD_ELF 147#define CONFIG_CMD_EXT2 148#define CONFIG_CMD_IDE 149#define CONFIG_CMD_JFFS2 150#define CONFIG_CMD_SNTP 151 152 153#define CONFIG_NETCONSOLE 154 155 156/* 157 * Miscellaneous configurable options 158 */ 159#define CONFIG_SYS_LONGHELP /* undef to save memory */ 160 161#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 162#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 163 164#if defined(CONFIG_CMD_KGDB) 165#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 166#else 167#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 168#endif 169#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 170#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 171#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 172 173#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 174#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 175 176#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 177 178/* 179 * Low Level Configuration Settings 180 * (address mappings, register initial values, etc.) 181 * You should know what you are doing if you make changes here. 182 */ 183/*----------------------------------------------------------------------- 184 * Internal Memory Mapped Register 185 */ 186#define CONFIG_SYS_IMMR 0xFFF00000 187 188/*----------------------------------------------------------------------- 189 * Definitions for initial stack pointer and data area (in DPRAM) 190 */ 191#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 192#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 193#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 194#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 195 196/*----------------------------------------------------------------------- 197 * Start addresses for the final memory configuration 198 * (Set up by the startup code) 199 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 200 */ 201#define CONFIG_SYS_SDRAM_BASE 0x00000000 202#define CONFIG_SYS_FLASH_BASE 0x40000000 203#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 204#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 205#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ 206 207/* 208 * For booting Linux, the board info and command line data 209 * have to be in the first 8 MB of memory, since this is 210 * the maximum mapped by the Linux kernel during initialization. 211 */ 212#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 213 214/*----------------------------------------------------------------------- 215 * FLASH organization 216 */ 217/* use CFI flash driver */ 218#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 219#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 220#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 221#define CONFIG_SYS_FLASH_EMPTY_INFO 222#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 223#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 224#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 225 226#define CONFIG_ENV_IS_IN_FLASH 1 227#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 228#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ 229#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ 230 231/* Address and size of Redundant Environment Sector */ 232#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 233#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 234 235#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 236 237#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 238 239/*----------------------------------------------------------------------- 240 * Dynamic MTD partition support 241 */ 242#define CONFIG_CMD_MTDPARTS 243#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 244#define CONFIG_FLASH_CFI_MTD 245#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 246 247#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 248 "128k(dtb)," \ 249 "1920k(kernel)," \ 250 "5632(rootfs)," \ 251 "4m(data)" 252 253/*----------------------------------------------------------------------- 254 * Hardware Information Block 255 */ 256#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 257#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 258#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 259 260/*----------------------------------------------------------------------- 261 * Cache Configuration 262 */ 263#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 264#if defined(CONFIG_CMD_KGDB) 265#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 266#endif 267 268/*----------------------------------------------------------------------- 269 * SYPCR - System Protection Control 11-9 270 * SYPCR can only be written once after reset! 271 *----------------------------------------------------------------------- 272 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 273 */ 274#if defined(CONFIG_WATCHDOG) 275#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 276 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 277#else 278#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 279#endif 280 281/*----------------------------------------------------------------------- 282 * SIUMCR - SIU Module Configuration 11-6 283 *----------------------------------------------------------------------- 284 * PCMCIA config., multi-function pin tri-state 285 */ 286#ifndef CONFIG_CAN_DRIVER 287#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 288#else /* we must activate GPL5 in the SIUMCR for CAN */ 289#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 290#endif /* CONFIG_CAN_DRIVER */ 291 292/*----------------------------------------------------------------------- 293 * TBSCR - Time Base Status and Control 11-26 294 *----------------------------------------------------------------------- 295 * Clear Reference Interrupt Status, Timebase freezing enabled 296 */ 297#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 298 299/*----------------------------------------------------------------------- 300 * PISCR - Periodic Interrupt Status and Control 11-31 301 *----------------------------------------------------------------------- 302 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 303 */ 304#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 305 306/*----------------------------------------------------------------------- 307 * SCCR - System Clock and reset Control Register 15-27 308 *----------------------------------------------------------------------- 309 * Set clock output, timebase and RTC source and divider, 310 * power management and some other internal clocks 311 */ 312#define SCCR_MASK SCCR_EBDF11 313#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 314 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 315 SCCR_DFALCD00) 316 317/*----------------------------------------------------------------------- 318 * PCMCIA stuff 319 *----------------------------------------------------------------------- 320 * 321 */ 322#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 323#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 324#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 325#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 326#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 327#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 328#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 329#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 330 331/*----------------------------------------------------------------------- 332 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 333 *----------------------------------------------------------------------- 334 */ 335 336#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 337#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 338 339#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 340#undef CONFIG_IDE_LED /* LED for ide not supported */ 341#undef CONFIG_IDE_RESET /* reset for ide not supported */ 342 343#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 344#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 345 346#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 347 348#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 349 350/* Offset for data I/O */ 351#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 352 353/* Offset for normal register accesses */ 354#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 355 356/* Offset for alternate registers */ 357#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 358 359/*----------------------------------------------------------------------- 360 * 361 *----------------------------------------------------------------------- 362 * 363 */ 364#define CONFIG_SYS_DER 0 365 366/* 367 * Init Memory Controller: 368 * 369 * BR0/1 and OR0/1 (FLASH) 370 */ 371 372#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 373#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 374 375/* used to re-map FLASH both when starting from SRAM or FLASH: 376 * restrict access enough to keep SRAM working (if any) 377 * but not too much to meddle with FLASH accesses 378 */ 379#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 380#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 381 382/* 383 * FLASH timing: Default value of OR0 after reset 384 */ 385#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ 386 OR_SCY_15_CLK | OR_TRLX) 387 388#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 389#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 390#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 391 392#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 393#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 394#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 395 396/* 397 * BR2/3 and OR2/3 (SDRAM) 398 * 399 */ 400#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 401#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 402#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ 403 404/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 405#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 406 407#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 408#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 409 410#ifndef CONFIG_CAN_DRIVER 411#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 412#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 413#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 414#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 415#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 416#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 417#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 418 BR_PS_8 | BR_MS_UPMB | BR_V ) 419#endif /* CONFIG_CAN_DRIVER */ 420 421/* 422 * 4096 Rows from SDRAM example configuration 423 * 1000 factor s -> ms 424 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration 425 * 4 Number of refresh cycles per period 426 * 64 Refresh cycle in ms per number of rows 427 */ 428#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) 429 430/* 431 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) 432 * 433 * CPUclock(MHz) * 31.2 434 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 435 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 436 * 437 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us 438 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us 439 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us 440 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us 441 * 442 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will 443 * be met also in the default configuration, i.e. if environment variable 444 * 'cpuclk' is not set. 445 */ 446#define CONFIG_SYS_MAMR_PTA 97 447 448/* 449 * Memory Periodic Timer Prescaler Register (MPTPR) values. 450 */ 451/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ 452#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 453/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ 454#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 455 456/* 457 * MAMR settings for SDRAM 458 */ 459 460/* 8 column SDRAM */ 461#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 462 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 463 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 464/* 9 column SDRAM */ 465#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 466 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 467 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 468/* 10 column SDRAM */ 469#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 470 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ 471 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 472 473#define CONFIG_SCC1_ENET 474#define CONFIG_FEC_ENET 475#define CONFIG_ETHPRIME "SCC" 476 477/* pass open firmware flat tree */ 478#define CONFIG_OF_LIBFDT 1 479#define CONFIG_OF_BOARD_SETUP 1 480#define CONFIG_HWCONFIG 1 481 482#endif /* __CONFIG_H */ 483