1/* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef __CONFIG_H 9#define __CONFIG_H 10 11/* 12 * High Level Configuration Options 13 * (easy to change) 14 */ 15 16#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ 17#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ 18 19/* 20 * allowed and functional CONFIG_SYS_TEXT_BASE values: 21 * 0xfe000000 low boot at 0x00000100 (default board setting) 22 * 0x00100000 RAM load and test 23 */ 24#define CONFIG_SYS_TEXT_BASE 0xFE000000 25 26#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ 27 28#define CONFIG_BOARD_EARLY_INIT_R 29 30#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 31 32/* 33 * Serial console configuration 34 */ 35#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 36#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 37#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 38 39 40/* 41 * BOOTP options 42 */ 43#define CONFIG_BOOTP_BOOTFILESIZE 44#define CONFIG_BOOTP_BOOTPATH 45#define CONFIG_BOOTP_GATEWAY 46#define CONFIG_BOOTP_HOSTNAME 47 48 49/* 50 * Command line configuration. 51 */ 52#define CONFIG_CMD_ASKENV 53#define CONFIG_CMD_DATE 54#define CONFIG_CMD_DHCP 55#define CONFIG_CMD_IMMAP 56#define CONFIG_CMD_MII 57#define CONFIG_CMD_REGINFO 58#define CONFIG_CMD_SNTP 59 60 61/* 62 * MUST be low boot - HIGHBOOT is not supported anymore 63 */ 64#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ 65# define CONFIG_SYS_LOWBOOT 1 66# define CONFIG_SYS_LOWBOOT16 1 67#else 68# error "CONFIG_SYS_TEXT_BASE must be 0xFE000000" 69#endif 70 71/* 72 * Autobooting 73 */ 74#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 75 76#define CONFIG_PREBOOT "echo;" \ 77 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 78 "echo" 79 80#undef CONFIG_BOOTARGS 81 82#define CONFIG_EXTRA_ENV_SETTINGS \ 83 "netdev=eth0\0" \ 84 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 85 "nfsroot=${serverip}:${rootpath}\0" \ 86 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 87 "addip=setenv bootargs ${bootargs} " \ 88 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 89 ":${hostname}:${netdev}:off panic=1\0" \ 90 "flash_nfs=run nfsargs addip;" \ 91 "bootm ${kernel_addr}\0" \ 92 "flash_self=run ramargs addip;" \ 93 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 94 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 95 "rootpath=/opt/eldk/ppc_6xx\0" \ 96 "bootfile=/tftpboot/canmb/uImage\0" \ 97 "" 98 99#define CONFIG_BOOTCOMMAND "run flash_self" 100 101/* 102 * IPB Bus clocking configuration. 103 */ 104#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 105 106/* 107 * Flash configuration, expect one 16 Megabyte Bank at most 108 */ 109#define CONFIG_SYS_FLASH_BASE 0xFE000000 110#define CONFIG_SYS_FLASH_SIZE 0x02000000 111#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 112#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ 113 114#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 115#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 116 117#define CONFIG_FLASH_CFI_DRIVER 118#define CONFIG_SYS_FLASH_CFI 119#define CONFIG_SYS_FLASH_EMPTY_INFO 120 121/* 122 * Environment settings 123 */ 124#define CONFIG_ENV_IS_IN_FLASH 1 125#define CONFIG_ENV_OFFSET (2*128*1024) 126#define CONFIG_ENV_SIZE 0x2000 127#define CONFIG_ENV_SECT_SIZE (128*1024) 128 129/* 130 * Memory map 131 * 132 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 133 */ 134#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */ 135#define CONFIG_SYS_SDRAM_BASE 0x00000000 136#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 137 138/* Use SRAM until RAM will be available */ 139#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 140#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ 141 142 143#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 144#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 145 146#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 147#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 148# define CONFIG_SYS_RAMBOOT 1 149#endif 150 151#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 152#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 153#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 154 155/* 156 * Ethernet configuration 157 */ 158#define CONFIG_MPC5xxx_FEC 1 159#define CONFIG_MPC5xxx_FEC_MII100 160#define CONFIG_PHY_ADDR 0x0 161/* 162 * GPIO configuration: 163 * PSC1,2,3 predefined as UART 164 * PCI disabled 165 * Ethernet 100 with MD 166 */ 167#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058444 168 169/* 170 * Miscellaneous configurable options 171 */ 172#define CONFIG_SYS_LONGHELP /* undef to save memory */ 173#if defined(CONFIG_CMD_KGDB) 174# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 175#else 176# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 177#endif 178#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 179#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 180#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 181 182#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 183#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ 184 185#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ 186 187#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ 188 189#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 190#if defined(CONFIG_CMD_KGDB) 191# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 192#endif 193 194/* 195 * Various low-level settings 196 */ 197#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 198#define CONFIG_SYS_HID0_FINAL HID0_ICE 199 200#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 201#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 202#define CONFIG_SYS_BOOTCS_CFG 0x00047D01 203#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 204#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 205 206#define CONFIG_SYS_CS_BURST 0x00000000 207#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 208 209#define CONFIG_SYS_RESET_ADDRESS 0x7f000000 210 211#endif /* __CONFIG_H */ 212