LXR uboot/include/configs/katmai.h

   1/*
   2 * (C) Copyright 2007
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10/************************************************************************
  11 * katmai.h - configuration for AMCC Katmai (440SPe)
  12 ***********************************************************************/
  13
  14#ifndef __CONFIG_H
  15#define __CONFIG_H
  16
  17/*-----------------------------------------------------------------------
  18 * High Level Configuration Options
  19 *----------------------------------------------------------------------*/
  20#define CONFIG_KATMAI                   1       /* Board is Katmai      */
  21#define CONFIG_440                      1       /* ... PPC440 family    */
  22#define CONFIG_440SPE                   1       /* Specifc SPe support  */
  23#define CONFIG_440SPE_REVA              1       /* Support old Rev A.   */
  24#define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
  25#define CONFIG_SYS_4xx_RESET_TYPE       0x2     /* use chip reset on this board */
  26
  27#define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  28
  29/*
  30 * Enable this board for more than 2GB of SDRAM
  31 */
  32#define CONFIG_PHYS_64BIT
  33#define CONFIG_VERY_BIG_RAM
  34
  35/*
  36 * Include common defines/options for all AMCC eval boards
  37 */
  38#define CONFIG_HOSTNAME         katmai
  39#include "amcc-common.h"
  40
  41#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_pre_init          */
  42#undef  CONFIG_SHOW_BOOT_PROGRESS
  43
  44/*-----------------------------------------------------------------------
  45 * Base addresses -- Note these are effective addresses where the
  46 * actual resources get mapped (not physical addresses)
  47 *----------------------------------------------------------------------*/
  48#define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH       */
  49#define CONFIG_SYS_ISRAM_BASE           0x90000000      /* internal SRAM        */
  50
  51#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  52#define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  53#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  54
  55#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  56#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  57#define CONFIG_SYS_PCIE_BASE            0xe0000000      /* PCIe UTL regs */
  58
  59#define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  60#define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  61#define CONFIG_SYS_PCIE2_CFGBASE        0xc2000000
  62#define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  63#define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  64#define CONFIG_SYS_PCIE2_XCFGBASE       0xc3002000
  65
  66/* base address of inbound PCIe window */
  67#define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
  68
  69/* System RAM mapped to PCI space */
  70#define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
  71#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
  72#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  73
  74#define CONFIG_SYS_ACE_BASE             0xfe000000      /* Xilinx ACE controller - Compact Flash */
  75
  76/*-----------------------------------------------------------------------
  77 * Initial RAM & stack pointer (placed in internal SRAM)
  78 *----------------------------------------------------------------------*/
  79#define CONFIG_SYS_TEMP_STACK_OCM       1
  80#define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
  81#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Initial RAM address  */
  82#define CONFIG_SYS_INIT_RAM_SIZE        0x2000          /* Size of used area in RAM */
  83
  84#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  85#define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  86
  87/*-----------------------------------------------------------------------
  88 * Serial Port
  89 *----------------------------------------------------------------------*/
  90#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  91#undef CONFIG_SYS_EXT_SERIAL_CLOCK
  92
  93/*-----------------------------------------------------------------------
  94 * DDR SDRAM
  95 *----------------------------------------------------------------------*/
  96#define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
  97#define SPD_EEPROM_ADDRESS      {0x51, 0x52}    /* SPD i2c spd addresses*/
  98#define CONFIG_DDR_ECC          1       /* with ECC support             */
  99#define CONFIG_DDR_RQDC_FIXED   0x80000038 /* optimal value found by GDA*/
 100#undef  CONFIG_STRESS
 101
 102/*-----------------------------------------------------------------------
 103 * I2C
 104 *----------------------------------------------------------------------*/
 105#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 106
 107#define CONFIG_SYS_SPD_BUS_NUM          0       /* The I2C bus for SPD          */
 108
 109#define IIC0_BOOTPROM_ADDR      0x50
 110#define IIC0_ALT_BOOTPROM_ADDR  0x54
 111
 112#define CONFIG_SYS_I2C_MULTI_EEPROMS
 113#define CONFIG_SYS_I2C_EEPROM_ADDR      (0x50)
 114#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 115#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 116#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 117
 118/* I2C bootstrap EEPROM */
 119#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x50
 120#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 121#define CONFIG_4xx_CONFIG_BLOCKSIZE             8
 122
 123/* I2C RTC */
 124#define CONFIG_RTC_M41T11       1
 125#define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC          */
 126#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 127#define CONFIG_SYS_M41T11_BASE_YEAR     1900    /* play along with linux        */
 128
 129/* I2C DTT */
 130#define CONFIG_DTT_ADM1021      1       /* ADM1021 temp sensor support  */
 131#define CONFIG_SYS_DTT_BUS_NUM          1       /* The I2C bus for DTT          */
 132/*
 133 * standard dtt sensor configuration - bottom bit will determine local or
 134 * remote sensor of the ADM1021, the rest determines index into
 135 * CONFIG_SYS_DTT_ADM1021 array below.
 136 */
 137#define CONFIG_DTT_SENSORS      { 0, 1 }
 138
 139/*
 140 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
 141 * there will be one entry in this array for each two (dummy) sensors in
 142 * CONFIG_DTT_SENSORS.
 143 *
 144 * For Katmai board:
 145 * - only one ADM1021
 146 * - i2c addr 0x18
 147 * - conversion rate 0x02 = 0.25 conversions/second
 148 * - ALERT ouput disabled
 149 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
 150 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
 151 */
 152#define CONFIG_SYS_DTT_ADM1021          { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
 153
 154/*-----------------------------------------------------------------------
 155 * Environment
 156 *----------------------------------------------------------------------*/
 157#define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
 158
 159/*
 160 * Default environment variables
 161 */
 162#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 163        CONFIG_AMCC_DEF_ENV                                             \
 164        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 165        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 166        "kernel_addr=ff000000\0"                                        \
 167        "fdt_addr=ff1e0000\0"                                           \
 168        "ramdisk_addr=ff200000\0"                                       \
 169        "pciconfighost=1\0"                                             \
 170        "pcie_mode=RP:RP:RP\0"                                          \
 171        ""
 172
 173/*
 174 * Commands additional to the ones defined in amcc-common.h
 175 */
 176#define CONFIG_CMD_CHIP_CONFIG
 177#define CONFIG_CMD_DATE
 178#define CONFIG_CMD_ECCTEST
 179#define CONFIG_CMD_EXT2
 180#define CONFIG_CMD_FAT
 181#define CONFIG_CMD_PCI
 182#define CONFIG_CMD_SDRAM
 183#define CONFIG_CMD_SNTP
 184
 185#define CONFIG_IBM_EMAC4_V4     1       /* 440SPe has this EMAC version */
 186#define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 187#define CONFIG_HAS_ETH0
 188#define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 189#define CONFIG_PHY_RESET_DELAY  1000
 190#define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 191#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 192
 193/*-----------------------------------------------------------------------
 194 * FLASH related
 195 *----------------------------------------------------------------------*/
 196#define CONFIG_SYS_FLASH_CFI
 197#define CONFIG_FLASH_CFI_DRIVER
 198#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 199#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 200
 201#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 202#define CONFIG_SYS_MAX_FLASH_BANKS     1                    /* number of banks      */
 203#define CONFIG_SYS_MAX_FLASH_SECT       1024                /* sectors per device   */
 204
 205#undef  CONFIG_SYS_FLASH_CHECKSUM
 206#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 207#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 208
 209#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 210#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 211#define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 212
 213/* Address and size of Redundant Environment Sector     */
 214#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 215#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 216
 217/*-----------------------------------------------------------------------
 218 * PCI stuff
 219 *-----------------------------------------------------------------------
 220 */
 221/* General PCI */
 222#define CONFIG_PCI                      /* include pci support          */
 223#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 224#define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 225#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 226#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 227
 228/* Board-specific PCI */
 229#define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 230#undef  CONFIG_SYS_PCI_MASTER_INIT
 231
 232#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 233#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 234/* #define CONFIG_SYS_PCI_SUBSYS_ID     CONFIG_SYS_PCI_SUBSYS_DEVICEID */
 235
 236/*
 237 *  NETWORK Support (PCI):
 238 */
 239/* Support for Intel 82557/82559/82559ER chips. */
 240#define CONFIG_EEPRO100
 241
 242/*-----------------------------------------------------------------------
 243 * Xilinx System ACE support
 244 *----------------------------------------------------------------------*/
 245#define CONFIG_SYSTEMACE        1       /* Enable SystemACE support     */
 246#define CONFIG_SYS_SYSTEMACE_WIDTH      16      /* Data bus width is 16         */
 247#define CONFIG_SYS_SYSTEMACE_BASE       CONFIG_SYS_ACE_BASE
 248#define CONFIG_DOS_PARTITION    1
 249
 250/*-----------------------------------------------------------------------
 251 * External Bus Controller (EBC) Setup
 252 *----------------------------------------------------------------------*/
 253
 254/* Memory Bank 0 (Flash) initialization                                 */
 255#define CONFIG_SYS_EBC_PB0AP            (EBC_BXAP_BME_DISABLED      |           \
 256                                 EBC_BXAP_TWT_ENCODE(7)     |           \
 257                                 EBC_BXAP_BCE_DISABLE       |           \
 258                                 EBC_BXAP_BCT_2TRANS        |           \
 259                                 EBC_BXAP_CSN_ENCODE(0)     |           \
 260                                 EBC_BXAP_OEN_ENCODE(0)     |           \
 261                                 EBC_BXAP_WBN_ENCODE(0)     |           \
 262                                 EBC_BXAP_WBF_ENCODE(0)     |           \
 263                                 EBC_BXAP_TH_ENCODE(0)      |           \
 264                                 EBC_BXAP_RE_DISABLED       |           \
 265                                 EBC_BXAP_SOR_DELAYED       |           \
 266                                 EBC_BXAP_BEM_WRITEONLY     |           \
 267                                 EBC_BXAP_PEN_DISABLED)
 268#define CONFIG_SYS_EBC_PB0CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |   \
 269                                 EBC_BXCR_BS_16MB                    |  \
 270                                 EBC_BXCR_BU_RW                      |  \
 271                                 EBC_BXCR_BW_16BIT)
 272
 273/* Memory Bank 1 (Xilinx System ACE controller) initialization          */
 274#define CONFIG_SYS_EBC_PB1AP            (EBC_BXAP_BME_DISABLED      |           \
 275                                 EBC_BXAP_TWT_ENCODE(4)     |           \
 276                                 EBC_BXAP_BCE_DISABLE       |           \
 277                                 EBC_BXAP_BCT_2TRANS        |           \
 278                                 EBC_BXAP_CSN_ENCODE(0)     |           \
 279                                 EBC_BXAP_OEN_ENCODE(0)     |           \
 280                                 EBC_BXAP_WBN_ENCODE(0)     |           \
 281                                 EBC_BXAP_WBF_ENCODE(0)     |           \
 282                                 EBC_BXAP_TH_ENCODE(0)      |           \
 283                                 EBC_BXAP_RE_DISABLED       |           \
 284                                 EBC_BXAP_SOR_NONDELAYED    |           \
 285                                 EBC_BXAP_BEM_WRITEONLY     |           \
 286                                 EBC_BXAP_PEN_DISABLED)
 287#define CONFIG_SYS_EBC_PB1CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |    \
 288                                 EBC_BXCR_BS_1MB                    |   \
 289                                 EBC_BXCR_BU_RW                     |   \
 290                                 EBC_BXCR_BW_16BIT)
 291
 292/*-------------------------------------------------------------------------
 293 * Initialize EBC CONFIG -
 294 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 295 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 296 *-------------------------------------------------------------------------*/
 297#define CONFIG_SYS_EBC_CFG              (EBC_CFG_LE_UNLOCK    | \
 298                                 EBC_CFG_PTD_ENABLE   | \
 299                                 EBC_CFG_RTC_16PERCLK | \
 300                                 EBC_CFG_ATC_PREVIOUS | \
 301                                 EBC_CFG_DTC_PREVIOUS | \
 302                                 EBC_CFG_CTC_PREVIOUS | \
 303                                 EBC_CFG_OEO_PREVIOUS | \
 304                                 EBC_CFG_EMC_DEFAULT  | \
 305                                 EBC_CFG_PME_DISABLE  | \
 306                                 EBC_CFG_PR_16)
 307
 308/*-----------------------------------------------------------------------
 309 * GPIO Setup
 310 *----------------------------------------------------------------------*/
 311#define CONFIG_SYS_GPIO_PCIE_PRESENT0   17
 312#define CONFIG_SYS_GPIO_PCIE_PRESENT1   21
 313#define CONFIG_SYS_GPIO_PCIE_PRESENT2   23
 314#define CONFIG_SYS_GPIO_RS232_FORCEOFF  30
 315
 316#define CONFIG_SYS_PFC0         (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
 317                                 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
 318                                 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
 319                                 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
 320#define CONFIG_SYS_GPIO_OR              GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 321#define CONFIG_SYS_GPIO_TCR             GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 322#define CONFIG_SYS_GPIO_ODR             0
 323
 324#endif  /* __CONFIG_H */
 325