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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11
12#define CONFIG_405EP 1
13#define CONFIG_NEO 1
14
15#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
16
17
18
19
20#define CONFIG_HOSTNAME neo
21#define CONFIG_IDENT_STRING " neo 0.02"
22#include "amcc-common.h"
23
24#define CONFIG_BOARD_EARLY_INIT_F
25#define CONFIG_BOARD_EARLY_INIT_R
26#define CONFIG_MISC_INIT_R
27#define CONFIG_LAST_STAGE_INIT
28#define CONFIG_SYS_GENERIC_BOARD
29
30#define CONFIG_SYS_CLK_FREQ 33333333
31
32
33
34
35#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
36#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
37
38
39#define CONFIG_FIT
40#define CONFIG_FIT_VERBOSE
41#define CONFIG_FIT_DISABLE_SHA256
42
43#define CONFIG_ENV_IS_IN_FLASH
44
45
46
47
48#define CONFIG_EXTRA_ENV_SETTINGS \
49 CONFIG_AMCC_DEF_ENV \
50 CONFIG_AMCC_DEF_ENV_POWERPC \
51 CONFIG_AMCC_DEF_ENV_NOR_UPD \
52 "kernel_addr=fc000000\0" \
53 "fdt_addr=fc1e0000\0" \
54 "ramdisk_addr=fc200000\0" \
55 ""
56
57#define CONFIG_PHY_ADDR 4
58#define CONFIG_HAS_ETH0
59#define CONFIG_HAS_ETH1
60#define CONFIG_PHY1_ADDR 0xc
61#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
62
63
64
65
66#define CONFIG_CMD_DTT
67#undef CONFIG_CMD_DHCP
68#undef CONFIG_CMD_DIAG
69#undef CONFIG_CMD_EEPROM
70#undef CONFIG_CMD_ELF
71#undef CONFIG_CMD_I2C
72#undef CONFIG_CMD_IRQ
73
74
75
76
77#define CONFIG_SDRAM_BANK0 1
78
79
80#define CONFIG_SYS_SDRAM_CL 3
81#define CONFIG_SYS_SDRAM_tRP 20
82#define CONFIG_SYS_SDRAM_tRC 66
83#define CONFIG_SYS_SDRAM_tRCD 20
84#define CONFIG_SYS_SDRAM_tRFC 66
85
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90
91
92
93
94
95#define CONFIG_CONS_INDEX 1
96#define CONFIG_SYS_NS16550
97#define CONFIG_SYS_NS16550_SERIAL
98#define CONFIG_SYS_NS16550_REG_SIZE 1
99#define CONFIG_SYS_NS16550_CLK get_serial_clock()
100
101#undef CONFIG_SYS_EXT_SERIAL_CLOCK
102#undef CONFIG_SYS_405_UART_ERRATA_59
103#define CONFIG_SYS_BASE_BAUD 691200
104
105
106
107
108#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
109
110
111#define CONFIG_RTC_DS1337
112#define CONFIG_SYS_I2C_RTC_ADDR 0x68
113
114
115#define CONFIG_DTT_LM63 1
116#define CONFIG_DTT_SENSORS { 0 }
117#define CONFIG_DTT_PWM_LOOKUPTABLE \
118 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
119#define CONFIG_DTT_TACH_LIMIT 0xa10
120
121
122
123
124#define CONFIG_SYS_FLASH_CFI
125#define CONFIG_FLASH_CFI_DRIVER
126
127#define CONFIG_SYS_FLASH_BASE 0xFC000000
128#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
129
130#define CONFIG_SYS_MAX_FLASH_BANKS 1
131#define CONFIG_SYS_MAX_FLASH_SECT 512
132
133#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
134#define CONFIG_SYS_FLASH_WRITE_TOUT 500
135
136#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
137
138#define CONFIG_SYS_FLASH_EMPTY_INFO
139#define CONFIG_SYS_FLASH_QUIET_TEST 1
140
141#ifdef CONFIG_ENV_IS_IN_FLASH
142#define CONFIG_ENV_SECT_SIZE 0x20000
143#define CONFIG_ENV_ADDR 0xFFF00000
144#define CONFIG_ENV_SIZE 0x20000
145
146
147#define CONFIG_ENV_ADDR_REDUND 0xFFF20000
148#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
149#endif
150
151
152
153
154#define CONFIG_SYS_4xx_GPIO_TABLE { \
155{ \
156 \
157{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
158{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
159{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
160{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
161{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
162{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
163{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
164{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
165{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
166{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
167{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
168{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
169{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
170{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
171{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
172{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
173{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
174{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
175{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
176{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
177{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
178{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
179{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
180{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
181{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
182{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
183{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
184{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
185{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
186{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
187{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
188{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
189} \
190}
191
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193
194
195
196#define CONFIG_SYS_TEMP_STACK_OCM 1
197
198
199#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
200#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
201#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
202#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
203
204#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
205#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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210
211
212#define CONFIG_SYS_EBC_PB0AP 0x92015480
213#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
214
215
216#define CONFIG_SYS_EBC_PB1AP 0x92015480
217#define CONFIG_SYS_EBC_PB1CR 0xFB85A000
218
219
220#define CONFIG_SYS_FPGA0_BASE 0x7f100000
221#define CONFIG_SYS_EBC_PB2AP 0x92015480
222#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
223
224#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
225
226#define CONFIG_SYS_FPGA_COUNT 1
227
228#define CONFIG_SYS_FPGA_PTR \
229 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
230
231#define CONFIG_SYS_FPGA_COMMON
232
233
234#define CONFIG_SYS_LATCH_BASE 0x7f200000
235#define CONFIG_SYS_EBC_PB3AP 0x92015480
236#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
237
238#define CONFIG_SYS_LATCH0_RESET 0xffff
239#define CONFIG_SYS_LATCH0_BOOT 0xffff
240#define CONFIG_SYS_LATCH1_RESET 0xffbf
241#define CONFIG_SYS_LATCH1_BOOT 0xffff
242
243#endif
244