LXR uboot/include/configs/pcs440ep.h

   1/*
   2 * (C) Copyright 2006
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/************************************************************************
   9 * pcs440ep.h - configuration for PCS440EP board
  10 ***********************************************************************/
  11#ifndef __CONFIG_H
  12#define __CONFIG_H
  13
  14
  15/* new uImage format support */
  16#define CONFIG_FIT              1
  17#define CONFIG_OF_LIBFDT        1
  18#define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
  19
  20/*-----------------------------------------------------------------------
  21 * High Level Configuration Options
  22 *----------------------------------------------------------------------*/
  23#define CONFIG_PCS440EP         1       /* Board is PCS440EP            */
  24#define CONFIG_440EP            1       /* Specific PPC440EP support    */
  25#define CONFIG_440              1       /* ... PPC440 family            */
  26
  27#define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  28
  29#define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  30
  31#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  32#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  33
  34/*-----------------------------------------------------------------------
  35 * Base addresses -- Note these are effective addresses where the
  36 * actual resources get mapped (not physical addresses)
  37 *----------------------------------------------------------------------*/
  38#define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384 kB for Monitor   */
  39#define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Reserve 256 kB for malloc()  */
  40#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
  41#define CONFIG_SYS_SDRAM_BASE           0x00000000          /* _must_ be 0      */
  42#define CONFIG_SYS_FLASH_BASE           0xfff00000          /* start of FLASH   */
  43#define CONFIG_SYS_PCI_MEMBASE          0xa0000000          /* mapped pci memory*/
  44#define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  45#define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  46#define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  47
  48/*Don't change either of these*/
  49#define CONFIG_SYS_PCI_BASE             0xe0000000          /* internal PCI regs*/
  50/*Don't change either of these*/
  51
  52#define CONFIG_SYS_USB_DEVICE          0x50000000
  53#define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
  54
  55/*-----------------------------------------------------------------------
  56 * Initial RAM & stack pointer (placed in SDRAM)
  57 *----------------------------------------------------------------------*/
  58#define CONFIG_SYS_INIT_RAM_DCACHE      1               /* d-cache as init ram  */
  59#define CONFIG_SYS_INIT_RAM_ADDR        0x70000000              /* DCache       */
  60#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  61#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  62#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  63
  64/*-----------------------------------------------------------------------
  65 * Serial Port
  66 *----------------------------------------------------------------------*/
  67#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  68#define CONFIG_SYS_NS16550
  69#define CONFIG_SYS_NS16550_SERIAL
  70#define CONFIG_SYS_NS16550_REG_SIZE     1
  71#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  72#undef CONFIG_SYS_EXT_SERIAL_CLOCK              /* no external clk used         */
  73#define CONFIG_BAUDRATE         115200
  74
  75#define CONFIG_SYS_BAUDRATE_TABLE  \
  76    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  77
  78/*-----------------------------------------------------------------------
  79 * Environment
  80 *----------------------------------------------------------------------*/
  81#define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  82
  83/*-----------------------------------------------------------------------
  84 * FLASH related
  85 *----------------------------------------------------------------------*/
  86#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
  87#define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
  88
  89#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
  90#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
  91
  92#define CONFIG_SYS_FLASH_WORD_SIZE      unsigned char   /* flash word size (width)      */
  93#define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
  94#define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
  95
  96#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
  97
  98#ifdef CONFIG_ENV_IS_IN_FLASH
  99#define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector          */
 100#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 101#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 102
 103#define CONFIG_ENV_OVERWRITE    1
 104
 105/* Address and size of Redundant Environment Sector     */
 106#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 107#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 108#endif /* CONFIG_ENV_IS_IN_FLASH */
 109
 110#define ENV_NAME_REVLEV "revision_level"
 111#define ENV_NAME_SOLDER "solder_switch"
 112#define ENV_NAME_DIP    "dip"
 113
 114/*-----------------------------------------------------------------------
 115 * DDR SDRAM
 116 *----------------------------------------------------------------------*/
 117#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
 118#undef CONFIG_DDR_ECC                   /* don't use ECC                        */
 119#define SPD_EEPROM_ADDRESS      {0x50}
 120#define CONFIG_PROG_SDRAM_TLB   1
 121
 122/*-----------------------------------------------------------------------
 123 * I2C
 124 *----------------------------------------------------------------------*/
 125#define CONFIG_SYS_I2C
 126#define CONFIG_SYS_I2C_PPC4XX
 127#define CONFIG_SYS_I2C_PPC4XX_CH0
 128#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 129#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 130
 131#define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa4>>1)
 132#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 133#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 134#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 135
 136#define CONFIG_PREBOOT  "echo;" \
 137        "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 138        "echo"
 139
 140#undef  CONFIG_BOOTARGS
 141
 142#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 143        "netdev=eth0\0"                                                 \
 144        "hostname=pcs440ep\0"                                           \
 145        "use_eeprom_ethaddr=default\0"                                  \
 146        "cs_test=off\0"                                                 \
 147        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 148                "nfsroot=${serverip}:${rootpath}\0"                     \
 149        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 150        "addip=setenv bootargs ${bootargs} "                            \
 151                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 152                ":${hostname}:${netdev}:off panic=1\0"                  \
 153        "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 154        "flash_nfs=run nfsargs addip addtty;"                           \
 155                "bootm ${kernel_addr}\0"                                \
 156        "flash_self=run ramargs addip addtty;"                          \
 157                "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 158        "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 159                "bootm\0"                                               \
 160        "rootpath=/opt/eldk/ppc_4xx\0"                                  \
 161        "bootfile=/tftpboot/pcs440ep/uImage\0"                          \
 162        "kernel_addr=FFF00000\0"                                        \
 163        "ramdisk_addr=FFF00000\0"                                       \
 164        "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0"              \
 165        "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"   \
 166                "cp.b 100000 FFFA0000 60000\0"                          \
 167        "upd=run load update\0"                                         \
 168        ""
 169#define CONFIG_BOOTCOMMAND      "run flash_self"
 170
 171#if 0
 172#define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 173#else
 174#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 175#endif
 176
 177/* check U-Boot image with SHA1 sum */
 178#define CONFIG_SHA1_CHECK_UB_IMG        1
 179#define CONFIG_SHA1_START               CONFIG_SYS_MONITOR_BASE
 180#define CONFIG_SHA1_LEN                 CONFIG_SYS_MONITOR_LEN
 181
 182/*-----------------------------------------------------------------------
 183 * Definitions for status LED
 184 */
 185#define CONFIG_STATUS_LED       1       /* Status LED enabled           */
 186#define CONFIG_BOARD_SPECIFIC_LED       1
 187
 188#define STATUS_LED_BIT          0x08                    /* DIAG1 is on GPIO_PPC_1 */
 189#define STATUS_LED_PERIOD       ((CONFIG_SYS_HZ / 2) / 5)       /* blink at 5 Hz */
 190#define STATUS_LED_STATE        STATUS_LED_OFF
 191#define STATUS_LED_BIT1         0x04                    /* DIAG2 is on GPIO_PPC_2 */
 192#define STATUS_LED_PERIOD1      ((CONFIG_SYS_HZ / 2) / 5)       /* blink at 5 Hz */
 193#define STATUS_LED_STATE1       STATUS_LED_ON
 194#define STATUS_LED_BIT2         0x02                    /* DIAG3 is on GPIO_PPC_3 */
 195#define STATUS_LED_PERIOD2      ((CONFIG_SYS_HZ / 2) / 5)       /* blink at 5 Hz */
 196#define STATUS_LED_STATE2       STATUS_LED_OFF
 197#define STATUS_LED_BIT3         0x01                    /* DIAG4 is on GPIO_PPC_4 */
 198#define STATUS_LED_PERIOD3      ((CONFIG_SYS_HZ / 2) / 5)       /* blink at 5 Hz */
 199#define STATUS_LED_STATE3       STATUS_LED_OFF
 200
 201#define CONFIG_SHOW_BOOT_PROGRESS       1
 202
 203#define CONFIG_BAUDRATE         115200
 204
 205#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 206#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 207
 208#define CONFIG_PPC4xx_EMAC
 209#define CONFIG_MII              1       /* MII PHY management           */
 210#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 211#define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 212#define CONFIG_PHY1_ADDR        2
 213
 214#define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 215
 216#define CONFIG_NETCONSOLE               /* include NetConsole support   */
 217
 218/* Partitions */
 219#define CONFIG_MAC_PARTITION
 220#define CONFIG_DOS_PARTITION
 221#define CONFIG_ISO_PARTITION
 222
 223#ifdef CONFIG_440EP
 224/* USB */
 225#define CONFIG_USB_OHCI
 226#define CONFIG_USB_STORAGE
 227
 228/*Comment this out to enable USB 1.1 device*/
 229#define USB_2_0_DEVICE
 230#endif /*CONFIG_440EP*/
 231
 232#ifdef DEBUG
 233#define CONFIG_PANIC_HANG
 234#else
 235#define CONFIG_HW_WATCHDOG                      /* watchdog */
 236#endif
 237
 238
 239/*
 240 * BOOTP options
 241 */
 242#define CONFIG_BOOTP_BOOTFILESIZE
 243#define CONFIG_BOOTP_BOOTPATH
 244#define CONFIG_BOOTP_GATEWAY
 245#define CONFIG_BOOTP_HOSTNAME
 246
 247
 248/*
 249 * Command line configuration.
 250 */
 251#define CONFIG_CMD_ASKENV
 252#define CONFIG_CMD_DHCP
 253#define CONFIG_CMD_DIAG
 254#define CONFIG_CMD_EEPROM
 255#define CONFIG_CMD_ELF
 256#define CONFIG_CMD_EXT2
 257#define CONFIG_CMD_FAT
 258#define CONFIG_CMD_I2C
 259#define CONFIG_CMD_IDE
 260#define CONFIG_CMD_IRQ
 261#define CONFIG_CMD_MII
 262#define CONFIG_CMD_PCI
 263#define CONFIG_CMD_PING
 264#define CONFIG_CMD_REGINFO
 265#define CONFIG_CMD_REISER
 266#define CONFIG_CMD_SDRAM
 267#define CONFIG_CMD_USB
 268
 269#define CONFIG_SUPPORT_VFAT
 270
 271/*
 272 * Miscellaneous configurable options
 273 */
 274#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 275#if defined(CONFIG_CMD_KGDB)
 276#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 277#else
 278#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 279#endif
 280#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 281#define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 282#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 283
 284#define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on           */
 285#define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM        */
 286
 287#define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 288#define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 289#define CONFIG_LYNXKDI          1       /* support kdi files            */
 290
 291/*-----------------------------------------------------------------------
 292 * PCI stuff
 293 *-----------------------------------------------------------------------
 294 */
 295/* General PCI */
 296#define CONFIG_PCI                      /* include pci support          */
 297#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 298#undef  CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
 299#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 300#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 301
 302/* Board-specific PCI */
 303#define CONFIG_SYS_PCI_TARGET_INIT
 304#define CONFIG_SYS_PCI_MASTER_INIT
 305
 306#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 307#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe   /* Whatever */
 308
 309/*
 310 * For booting Linux, the board info and command line data
 311 * have to be in the first 8 MB of memory, since this is
 312 * the maximum mapped by the Linux kernel during initialization.
 313 */
 314#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 315
 316/*-----------------------------------------------------------------------
 317 * External Bus Controller (EBC) Setup
 318 *----------------------------------------------------------------------*/
 319#define FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank #0        */
 320#define FLASH_BASE1_PRELIM      0xFFF80000      /* FLASH bank #1        */
 321
 322#define CONFIG_SYS_FLASH                FLASH_BASE0_PRELIM
 323#define CONFIG_SYS_SRAM         0xF1000000
 324#define CONFIG_SYS_FPGA         0xF2000000
 325#define CONFIG_SYS_CF1                  0xF0000000
 326#define CONFIG_SYS_CF2                  0xF0100000
 327
 328/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 329#define CONFIG_SYS_EBC_PB0AP            0x02010000      /* TWT=4,OEN=1                  */
 330#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit   */
 331
 332/* Memory Bank 1 (SRAM) initialization                                          */
 333#define CONFIG_SYS_EBC_PB1AP            0x01810040      /* TWT=3,OEN=1,BEM=1            */
 334#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit   */
 335
 336/* Memory Bank 2 (FPGA) initialization                                          */
 337#define CONFIG_SYS_EBC_PB2AP            0x01010440      /* TWT=2,OEN=1,TH=2,BEM=1       */
 338#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit   */
 339
 340/* Memory Bank 3 (CompactFlash) initialization                                  */
 341#define CONFIG_SYS_EBC_PB3AP            0x080BD400
 342#define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit    */
 343
 344/* Memory Bank 4 (CompactFlash) initialization                                  */
 345#define CONFIG_SYS_EBC_PB4AP            0x080BD400
 346#define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit    */
 347
 348/*-----------------------------------------------------------------------
 349 * PPC440 GPIO Configuration
 350 */
 351#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out                  GPIO     Alternate1      Alternate2   Alternate3 */ \
 352{                                                                                       \
 353/* GPIO Core 0 */                                                                       \
 354{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO0    EBC_ADDR(7)     DMA_REQ(2)      */ \
 355{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO1    EBC_ADDR(6)     DMA_ACK(2)      */      \
 356{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO2    EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 357{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO3    EBC_ADDR(4)     DMA_REQ(3)      */      \
 358{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO4    EBC_ADDR(3)     DMA_ACK(3)      */      \
 359{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO5    EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 360{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6    EBC_CS_N(1)                     */      \
 361{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7    EBC_CS_N(2)                     */      \
 362{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8    EBC_CS_N(3)                     */      \
 363{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9    EBC_CS_N(4)                     */      \
 364{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO10   EBC_CS_N(5)                     */      \
 365{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO11   EBC_BUS_ERR                     */      \
 366{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12   ZII_p0Rxd(0)                    */      \
 367{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13   ZII_p0Rxd(1)                    */      \
 368{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14   ZII_p0Rxd(2)                    */      \
 369{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15   ZII_p0Rxd(3)                    */      \
 370{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16   ZII_p0Txd(0)                    */      \
 371{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17   ZII_p0Txd(1)                    */      \
 372{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18   ZII_p0Txd(2)                    */      \
 373{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19   ZII_p0Txd(3)                    */      \
 374{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20   ZII_p0Rx_er                     */      \
 375{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21   ZII_p0Rx_dv                     */      \
 376{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22   ZII_p0RxCrs                     */      \
 377{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23   ZII_p0Tx_er                     */      \
 378{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24   ZII_p0Tx_en                     */      \
 379{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25   ZII_p0Col                       */      \
 380{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO26                   USB2D_RXVALID   */      \
 381{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO27   EXT_EBC_REQ     USB2D_RXERROR   */      \
 382{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO28                   USB2D_TXVALID   */      \
 383{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO29   EBC_EXT_HDLA    USB2D_PAD_SUSPNDM */    \
 384{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO30   EBC_EXT_ACK     USB2D_XCVRSELECT*/      \
 385{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO31   EBC_EXR_BUSREQ  USB2D_TERMSELECT*/      \
 386},                                                                                      \
 387{                                                                                       \
 388/* GPIO Core 1 */                                                                       \
 389{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO32   USB2D_OPMODE0                   */      \
 390{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO33   USB2D_OPMODE1                   */      \
 391{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34   UART0_DCD_N     UART1_DSR_CTS_N UART2_SOUT*/ \
 392{GPIO1_BASE, GPIO_IN,  GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35   UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 393{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36   UART0_8PIN_CTS_N                UART3_SIN*/ \
 394{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37   UART0_RTS_N                     */      \
 395{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38   UART0_DTR_N     UART1_SOUT      */      \
 396{GPIO1_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39   UART0_RI_N      UART1_SIN       */      \
 397{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40   UIC_IRQ(0)                      */      \
 398{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41   UIC_IRQ(1)                      */      \
 399{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42   UIC_IRQ(2)                      */      \
 400{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43   UIC_IRQ(3)                      */      \
 401{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44   UIC_IRQ(4)      DMA_ACK(1)      */      \
 402{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO45   UIC_IRQ(6)      DMA_EOT/TC(1)   */      \
 403{GPIO1_BASE, GPIO_BI,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO46   UIC_IRQ(7)      DMA_REQ(0)      */      \
 404{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO47   UIC_IRQ(8)      DMA_ACK(0)      */      \
 405{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO48   UIC_IRQ(9)      DMA_EOT/TC(0)   */      \
 406{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO49  Unselect via TraceSelect Bit     */      \
 407{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO50  Unselect via TraceSelect Bit     */      \
 408{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO51  Unselect via TraceSelect Bit     */      \
 409{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO52  Unselect via TraceSelect Bit     */      \
 410{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO53  Unselect via TraceSelect Bit     */      \
 411{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO54  Unselect via TraceSelect Bit     */      \
 412{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO55  Unselect via TraceSelect Bit     */      \
 413{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO56  Unselect via TraceSelect Bit     */      \
 414{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO57  Unselect via TraceSelect Bit     */      \
 415{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO58  Unselect via TraceSelect Bit     */      \
 416{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO59  Unselect via TraceSelect Bit     */      \
 417{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO60  Unselect via TraceSelect Bit     */      \
 418{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO61  Unselect via TraceSelect Bit     */      \
 419{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO62  Unselect via TraceSelect Bit     */      \
 420{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO63  Unselect via TraceSelect Bit     */      \
 421}                                                                                       \
 422}
 423
 424#if defined(CONFIG_CMD_KGDB)
 425#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 426#endif
 427
 428/*-----------------------------------------------------------------------
 429 * IDE/ATA stuff Supports IDE harddisk
 430 *-----------------------------------------------------------------------
 431 */
 432
 433#undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 434
 435#undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 436#undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 437
 438#define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 439#define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 2 drives per IDE bus    */
 440
 441#define CONFIG_IDE_PREINIT      1
 442#define CONFIG_IDE_RESET        1
 443
 444#define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 445
 446#define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF1
 447
 448/* Offset for data I/O                  */
 449#define CONFIG_SYS_ATA_DATA_OFFSET      0
 450
 451/* Offset for normal register accesses  */
 452#define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 453
 454/* Offset for alternate registers       */
 455#define CONFIG_SYS_ATA_ALT_OFFSET       (0x0000)
 456
 457#endif  /* __CONFIG_H */
 458