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13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#define CONFIG_SYS_GENERIC_BOARD
17
18
19
20
21#ifdef CONFIG_PCI
22#define CONFIG_PCI_INDIRECT_BRIDGE
23#define CONFIG_PCI1
24#endif
25
26#ifdef CONFIG_66
27#define CONFIG_SYS_CLK_DIV 1
28#endif
29
30#ifdef CONFIG_33
31#define CONFIG_SYS_CLK_DIV 2
32#endif
33
34#ifdef CONFIG_PCIE
35#define CONFIG_PCIE1
36#endif
37
38
39
40
41#define CONFIG_BOOKE 1
42#define CONFIG_E500 1
43#define CONFIG_MPC8548 1
44#define CONFIG_SBC8548 1
45
46
47
48
49
50#undef CONFIG_SYS_ALT_BOOT
51
52#ifndef CONFIG_SYS_TEXT_BASE
53#ifdef CONFIG_SYS_ALT_BOOT
54#define CONFIG_SYS_TEXT_BASE 0xfff00000
55#else
56#define CONFIG_SYS_TEXT_BASE 0xfffa0000
57#endif
58#endif
59
60#undef CONFIG_RIO
61
62#ifdef CONFIG_PCI
63#define CONFIG_FSL_PCI_INIT
64#define CONFIG_SYS_PCI_64BIT 1
65#endif
66#ifdef CONFIG_PCIE1
67#define CONFIG_FSL_PCIE_RESET 1
68#endif
69
70#define CONFIG_TSEC_ENET
71#define CONFIG_ENV_OVERWRITE
72
73#define CONFIG_INTERRUPTS
74
75#define CONFIG_FSL_LAW 1
76
77
78
79
80#ifndef CONFIG_SYS_CLK_DIV
81#define CONFIG_SYS_CLK_DIV 1
82#endif
83#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
84
85
86
87
88#define CONFIG_L2_CACHE
89#define CONFIG_BTB
90
91
92
93
94#define CONFIG_ENABLE_36BIT_PHYS 1
95
96#define CONFIG_BOARD_EARLY_INIT_F 1
97
98#undef CONFIG_SYS_DRAM_TEST
99#define CONFIG_SYS_MEMTEST_START 0x00200000
100#define CONFIG_SYS_MEMTEST_END 0x00400000
101
102#define CONFIG_SYS_CCSRBAR 0xe0000000
103#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
104
105
106#define CONFIG_SYS_FSL_DDR2
107#undef CONFIG_FSL_DDR_INTERACTIVE
108#undef CONFIG_DDR_ECC
109
110
111
112
113
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115
116
117#undef CONFIG_SPD_EEPROM
118#undef CONFIG_DDR_SPD
119
120#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
121#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
122
123#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
124#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
125#define CONFIG_VERY_BIG_RAM
126
127#define CONFIG_NUM_DDR_CONTROLLERS 1
128#define CONFIG_DIMM_SLOTS_PER_CTLR 1
129#define CONFIG_CHIP_SELECTS_PER_CTRL 2
130
131
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134
135
136#define SPD_EEPROM_ADDRESS 0x51
137#define ALT_SPD_EEPROM_ADDRESS 0x53
138
139
140
141
142#ifndef CONFIG_SPD_EEPROM
143 #define CONFIG_SYS_SDRAM_SIZE 256
144 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
145#endif
146
147#undef CONFIG_CLOCKS_IN_MHZ
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176
177#define CONFIG_SYS_BR0_8M 0xff800801
178#define CONFIG_SYS_BR0_64M 0xfc001801
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194
195#define CONFIG_SYS_BR6_8M 0xef800801
196#define CONFIG_SYS_BR6_64M 0xec001801
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216#define CONFIG_SYS_OR0_8M 0xff806e65
217#define CONFIG_SYS_OR0_64M 0xfc006e65
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235
236#define CONFIG_SYS_OR6_8M 0xff806e65
237#define CONFIG_SYS_OR6_64M 0xfc006e65
238
239#ifndef CONFIG_SYS_ALT_BOOT
240#define CONFIG_SYS_BOOT_BLOCK 0xff800000
241#define CONFIG_SYS_ALT_FLASH 0xec000000
242
243#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M
244#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M
245
246#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M
247#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M
248#else
249#define CONFIG_SYS_BOOT_BLOCK 0xfc000000
250#define CONFIG_SYS_ALT_FLASH 0xef800000
251
252#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M
253#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M
254
255#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M
256#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M
257#endif
258
259#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
260#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
261 CONFIG_SYS_ALT_FLASH}
262#define CONFIG_SYS_MAX_FLASH_BANKS 2
263#define CONFIG_SYS_MAX_FLASH_SECT 256
264#undef CONFIG_SYS_FLASH_CHECKSUM
265#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
266#define CONFIG_SYS_FLASH_WRITE_TOUT 500
267
268#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
269
270#define CONFIG_FLASH_CFI_DRIVER
271#define CONFIG_SYS_FLASH_CFI
272#define CONFIG_SYS_FLASH_EMPTY_INFO
273
274
275
276#define CONFIG_SYS_BR5_PRELIM 0xf8000801
277#define CONFIG_SYS_OR5_PRELIM 0xff006e65
278#define CONFIG_SYS_EPLD_BASE 0xf8000000
279#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
280#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
281#define CONFIG_SYS_BD_REV 0xf8300000
282#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
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291#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
292#define CONFIG_SYS_LBC_SDRAM_SIZE 128
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310#define CONFIG_SYS_BR3_PRELIM 0xf0001861
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326#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
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343
344#define CONFIG_SYS_BR4_PRELIM 0xf4001861
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360#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
361
362#define CONFIG_SYS_LBC_LCRR 0x00000002
363#define CONFIG_SYS_LBC_LBCR 0x00000000
364#define CONFIG_SYS_LBC_LSRT 0x20000000
365#define CONFIG_SYS_LBC_MRTPR 0x00000000
366
367
368
369
370#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
371 | LSDMR_BSMA1516 \
372 | LSDMR_PRETOACT3 \
373 | LSDMR_ACTTORW3 \
374 | LSDMR_BUFCMD \
375 | LSDMR_BL8 \
376 | LSDMR_WRC2 \
377 | LSDMR_CL3 \
378 )
379
380#define CONFIG_SYS_LBC_LSDMR_PCHALL \
381 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
382#define CONFIG_SYS_LBC_LSDMR_ARFRSH \
383 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
384#define CONFIG_SYS_LBC_LSDMR_MRW \
385 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
386#define CONFIG_SYS_LBC_LSDMR_RFEN \
387 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
388
389#define CONFIG_SYS_INIT_RAM_LOCK 1
390#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
391#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
392
393#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
394
395#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
396#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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404
405#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
406#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
407
408
409#define CONFIG_CONS_INDEX 1
410#define CONFIG_SYS_NS16550
411#define CONFIG_SYS_NS16550_SERIAL
412#define CONFIG_SYS_NS16550_REG_SIZE 1
413#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
414
415#define CONFIG_SYS_BAUDRATE_TABLE \
416 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
417
418#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
419#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
420
421
422#define CONFIG_SYS_HUSH_PARSER
423
424
425#define CONFIG_OF_LIBFDT 1
426#define CONFIG_OF_BOARD_SETUP 1
427#define CONFIG_OF_STDOUT_VIA_ALIAS 1
428
429
430
431
432#define CONFIG_SYS_I2C
433#define CONFIG_SYS_I2C_FSL
434#define CONFIG_SYS_FSL_I2C_SPEED 400000
435#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
436#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
437#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
438
439
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441
442
443#define CONFIG_SYS_PCI_VIRT 0x80000000
444#define CONFIG_SYS_PCI_PHYS 0x80000000
445
446#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
447#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
448#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
449#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
450#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
451#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
452#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
453#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000
454
455#ifdef CONFIG_PCIE1
456#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
457#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
458#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
459#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
460#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
461#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
462#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
463#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
464#endif
465
466#ifdef CONFIG_RIO
467
468
469
470#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
471#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000
472#endif
473
474#if defined(CONFIG_PCI)
475
476#define CONFIG_PCI_PNP
477
478#undef CONFIG_EEPRO100
479#undef CONFIG_TULIP
480
481#define CONFIG_PCI_SCAN_SHOW
482
483#endif
484
485
486#if defined(CONFIG_TSEC_ENET)
487
488#define CONFIG_MII 1
489#define CONFIG_TSEC1 1
490#define CONFIG_TSEC1_NAME "eTSEC0"
491#define CONFIG_TSEC2 1
492#define CONFIG_TSEC2_NAME "eTSEC1"
493#undef CONFIG_MPC85XX_FEC
494
495#define TSEC1_PHY_ADDR 0x19
496#define TSEC2_PHY_ADDR 0x1a
497
498#define TSEC1_PHYIDX 0
499#define TSEC2_PHYIDX 0
500
501#define TSEC1_FLAGS TSEC_GIGABIT
502#define TSEC2_FLAGS TSEC_GIGABIT
503
504
505#define CONFIG_ETHPRIME "eTSEC0"
506#define CONFIG_PHY_GIGE 1
507#endif
508
509
510
511
512#define CONFIG_ENV_IS_IN_FLASH 1
513#define CONFIG_ENV_SIZE 0x2000
514#if CONFIG_SYS_TEXT_BASE == 0xfff00000
515#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
516#define CONFIG_ENV_SECT_SIZE 0x80000
517#elif CONFIG_SYS_TEXT_BASE == 0xfffa0000
518#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
519#define CONFIG_ENV_SECT_SIZE 0x20000
520#else
521#warning undefined environment size/location.
522#endif
523
524#define CONFIG_LOADS_ECHO 1
525#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
526
527
528
529
530#define CONFIG_BOOTP_BOOTFILESIZE
531#define CONFIG_BOOTP_BOOTPATH
532#define CONFIG_BOOTP_GATEWAY
533#define CONFIG_BOOTP_HOSTNAME
534
535
536
537
538
539#define CONFIG_CMD_PING
540#define CONFIG_CMD_I2C
541#define CONFIG_CMD_MII
542#define CONFIG_CMD_ELF
543#define CONFIG_CMD_REGINFO
544
545#if defined(CONFIG_PCI)
546 #define CONFIG_CMD_PCI
547#endif
548
549
550#undef CONFIG_WATCHDOG
551
552
553
554
555#define CONFIG_CMDLINE_EDITING
556#define CONFIG_AUTO_COMPLETE
557#define CONFIG_SYS_LONGHELP
558#define CONFIG_SYS_LOAD_ADDR 0x2000000
559#if defined(CONFIG_CMD_KGDB)
560#define CONFIG_SYS_CBSIZE 1024
561#else
562#define CONFIG_SYS_CBSIZE 256
563#endif
564#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
565#define CONFIG_SYS_MAXARGS 16
566#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
567
568
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571
572
573#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
574
575#if defined(CONFIG_CMD_KGDB)
576#define CONFIG_KGDB_BAUDRATE 230400
577#endif
578
579
580
581
582#if defined(CONFIG_TSEC_ENET)
583#define CONFIG_HAS_ETH0
584#define CONFIG_HAS_ETH1
585#endif
586
587#define CONFIG_IPADDR 192.168.0.55
588
589#define CONFIG_HOSTNAME sbc8548
590#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
591#define CONFIG_BOOTFILE "/uImage"
592#define CONFIG_UBOOTPATH /u-boot.bin
593
594#define CONFIG_SERVERIP 192.168.0.2
595#define CONFIG_GATEWAYIP 192.168.0.1
596#define CONFIG_NETMASK 255.255.255.0
597
598#define CONFIG_LOADADDR 1000000
599
600#define CONFIG_BOOTDELAY 10
601#undef CONFIG_BOOTARGS
602
603#define CONFIG_BAUDRATE 115200
604
605#define CONFIG_EXTRA_ENV_SETTINGS \
606"netdev=eth0\0" \
607"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
608"tftpflash=tftpboot $loadaddr $uboot; " \
609 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
610 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
611 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
612 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
613 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
614"consoledev=ttyS0\0" \
615"ramdiskaddr=2000000\0" \
616"ramdiskfile=uRamdisk\0" \
617"fdtaddr=c00000\0" \
618"fdtfile=sbc8548.dtb\0"
619
620#define CONFIG_NFSBOOTCOMMAND \
621 "setenv bootargs root=/dev/nfs rw " \
622 "nfsroot=$serverip:$rootpath " \
623 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
624 "console=$consoledev,$baudrate $othbootargs;" \
625 "tftp $loadaddr $bootfile;" \
626 "tftp $fdtaddr $fdtfile;" \
627 "bootm $loadaddr - $fdtaddr"
628
629
630#define CONFIG_RAMBOOTCOMMAND \
631 "setenv bootargs root=/dev/ram rw " \
632 "console=$consoledev,$baudrate $othbootargs;" \
633 "tftp $ramdiskaddr $ramdiskfile;" \
634 "tftp $loadaddr $bootfile;" \
635 "tftp $fdtaddr $fdtfile;" \
636 "bootm $loadaddr $ramdiskaddr $fdtaddr"
637
638#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
639
640#endif
641