LXR uboot/include/fsl

   1/*
   2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License
   6 * Version 2 as published by the Free Software Foundation.
   7 */
   8
   9#ifndef FSL_DDR_MAIN_H
  10#define FSL_DDR_MAIN_H
  11
  12#include <fsl_ddrc_version.h>
  13#include <fsl_ddr_sdram.h>
  14#include <fsl_ddr_dimm_params.h>
  15
  16#include <common_timing_params.h>
  17
  18#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
  19/* All controllers are for main memory */
  20#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       CONFIG_NUM_DDR_CONTROLLERS
  21#endif
  22
  23#ifdef CONFIG_SYS_FSL_DDR_LE
  24#define ddr_in32(a)     in_le32(a)
  25#define ddr_out32(a, v) out_le32(a, v)
  26#define ddr_setbits32(a, v)     setbits_le32(a, v)
  27#define ddr_clrbits32(a, v)     clrbits_le32(a, v)
  28#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
  29#else
  30#define ddr_in32(a)     in_be32(a)
  31#define ddr_out32(a, v) out_be32(a, v)
  32#define ddr_setbits32(a, v)     setbits_be32(a, v)
  33#define ddr_clrbits32(a, v)     clrbits_be32(a, v)
  34#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
  35#endif
  36
  37u32 fsl_ddr_get_version(unsigned int ctrl_num);
  38
  39#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
  40/*
  41 * Bind the main DDR setup driver's generic names
  42 * to this specific DDR technology.
  43 */
  44static __inline__ int
  45compute_dimm_parameters(const unsigned int ctrl_num,
  46                        const generic_spd_eeprom_t *spd,
  47                        dimm_params_t *pdimm,
  48                        unsigned int dimm_number)
  49{
  50        return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
  51}
  52#endif
  53
  54/*
  55 * Data Structures
  56 *
  57 * All data structures have to be on the stack
  58 */
  59#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
  60#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
  61
  62typedef struct {
  63        generic_spd_eeprom_t
  64           spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  65        struct dimm_params_s
  66           dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  67        memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
  68        common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
  69        fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
  70        unsigned int first_ctrl;
  71        unsigned int num_ctrls;
  72        unsigned long long mem_base;
  73        unsigned int dimm_slots_per_ctrl;
  74        int (*board_need_mem_reset)(void);
  75        void (*board_mem_reset)(void);
  76        void (*board_mem_de_reset)(void);
  77} fsl_ddr_info_t;
  78
  79/* Compute steps */
  80#define STEP_GET_SPD                 (1 << 0)
  81#define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
  82#define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
  83#define STEP_GATHER_OPTS             (1 << 3)
  84#define STEP_ASSIGN_ADDRESSES        (1 << 4)
  85#define STEP_COMPUTE_REGS            (1 << 5)
  86#define STEP_PROGRAM_REGS            (1 << 6)
  87#define STEP_ALL                     0xFFF
  88
  89unsigned long long
  90fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
  91                                       unsigned int size_only);
  92const char *step_to_string(unsigned int step);
  93
  94unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
  95                               const memctl_options_t *popts,
  96                               fsl_ddr_cfg_regs_t *ddr,
  97                               const common_timing_params_t *common_dimm,
  98                               const dimm_params_t *dimm_parameters,
  99                               unsigned int dbw_capacity_adjust,
 100                               unsigned int size_only);
 101unsigned int compute_lowest_common_dimm_parameters(
 102                                const unsigned int ctrl_num,
 103                                const dimm_params_t *dimm_params,
 104                                common_timing_params_t *outpdimm,
 105                                unsigned int number_of_dimms);
 106unsigned int populate_memctl_options(int all_dimms_registered,
 107                                memctl_options_t *popts,
 108                                dimm_params_t *pdimm,
 109                                unsigned int ctrl_num);
 110void check_interleaving_options(fsl_ddr_info_t *pinfo);
 111
 112unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
 113unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
 114unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
 115void fsl_ddr_set_lawbar(
 116                const common_timing_params_t *memctl_common_params,
 117                unsigned int memctl_interleaved,
 118                unsigned int ctrl_num);
 119void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 120                                 unsigned int last_ctrl);
 121
 122int fsl_ddr_interactive_env_var_exists(void);
 123unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
 124void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 125                     unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
 126
 127int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 128unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
 129void board_add_ram_info(int use_default);
 130
 131/* processor specific function */
 132void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 133                                   unsigned int ctrl_num, int step);
 134
 135/* board specific function */
 136int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 137                        unsigned int controller_number,
 138                        unsigned int dimm_number);
 139#endif
 140