LXR uboot/arch/nios2/include/asm/cache.h

   1/*
   2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
   3 * Scott McNutt <smcnutt@psyent.com>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef __ASM_NIOS2_CACHE_H_
   9#define __ASM_NIOS2_CACHE_H_
  10
  11extern void flush_dcache (unsigned long start, unsigned long size);
  12extern void flush_icache (unsigned long start, unsigned long size);
  13
  14/*
  15 * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32
  16 * bytes.  If the board configuration has not specified one we default to the
  17 * largest of these values for alignment of DMA buffers.
  18 */
  19#ifdef CONFIG_SYS_CACHELINE_SIZE
  20#define ARCH_DMA_MINALIGN       CONFIG_SYS_CACHELINE_SIZE
  21#else
  22#define ARCH_DMA_MINALIGN       32
  23#endif
  24
  25#endif /* __ASM_NIOS2_CACHE_H_ */
  26