1/* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */ 2/* 3 * SPDX-License-Identifier: GPL-2.0 IBM-pibs 4 */ 5/*----------------------------------------------------------------------------+ 6| 7| File Name: mal.h 8| 9| Function: Header file for the MAL (MADMAL) macro on the 405GP. 10| 11| Author: Mark Wisner 12| 13| Change Activity- 14| 15| Date Description of Change BY 16| --------- --------------------- --- 17| 29-Apr-99 Created MKW 18| 19+----------------------------------------------------------------------------*/ 20/*----------------------------------------------------------------------------+ 21| 17-Nov-03 Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com 22| Added register bit definitions to support multiple channels 23+----------------------------------------------------------------------------*/ 24#ifndef _mal_h_ 25#define _mal_h_ 26 27#if !defined(MAL_DCR_BASE) 28#define MAL_DCR_BASE 0x180 29#endif 30#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ 31#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */ 32#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ 33#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ 34#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */ 35#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/ 36#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */ 37#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/ 38#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ 39#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ 40#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/ 41#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */ 42#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */ 43#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */ 44#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */ 45#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */ 46#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */ 47#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */ 48#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */ 49#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ 50#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ 51#if defined(CONFIG_440GX) || \ 52 defined(CONFIG_460EX) || defined(CONFIG_460GT) 53#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */ 54#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */ 55#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */ 56#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/ 57#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/ 58#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ 59#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ 60#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ 61#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ 62#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ 63#endif /* CONFIG_440GX */ 64 65/* MADMAL transmit and receive status/control bits */ 66/* for COMMAC bits, refer to the COMMAC header file */ 67 68#define MAL_TX_CTRL_READY 0x8000 69#define MAL_TX_CTRL_WRAP 0x4000 70#define MAL_TX_CTRL_CM 0x2000 71#define MAL_TX_CTRL_LAST 0x1000 72#define MAL_TX_CTRL_INTR 0x0400 73 74#define MAL_RX_CTRL_EMPTY 0x8000 75#define MAL_RX_CTRL_WRAP 0x4000 76#define MAL_RX_CTRL_CM 0x2000 77#define MAL_RX_CTRL_LAST 0x1000 78#define MAL_RX_CTRL_FIRST 0x0800 79#define MAL_RX_CTRL_INTR 0x0400 80 81 /* Configuration Reg */ 82#define MAL_CR_MMSR 0x80000000 83#define MAL_CR_PLBP_1 0x00400000 /* lowsest is 00 */ 84#define MAL_CR_PLBP_2 0x00800000 85#define MAL_CR_PLBP_3 0x00C00000 /* highest */ 86#define MAL_CR_GA 0x00200000 87#define MAL_CR_OA 0x00100000 88#define MAL_CR_PLBLE 0x00080000 89#define MAL_CR_PLBLT_1 0x00040000 90#define MAL_CR_PLBLT_2 0x00020000 91#define MAL_CR_PLBLT_3 0x00010000 92#define MAL_CR_PLBLT_4 0x00008000 93#define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */ 94#define MAL_CR_PLBB 0x00004000 95#define MAL_CR_OPBBL 0x00000080 96#define MAL_CR_EOPIE 0x00000004 97#define MAL_CR_LEA 0x00000002 98#define MAL_CR_MSD 0x00000001 99 100 /* Error Status Reg */ 101#define MAL_ESR_EVB 0x80000000 102#define MAL_ESR_CID 0x40000000 103#define MAL_ESR_DE 0x00100000 104#define MAL_ESR_ONE 0x00080000 105#define MAL_ESR_OTE 0x00040000 106#define MAL_ESR_OSE 0x00020000 107#define MAL_ESR_PEIN 0x00010000 108 /* same bit position as the IER */ 109 /* VV VV */ 110#define MAL_ESR_DEI 0x00000010 111#define MAL_ESR_ONEI 0x00000008 112#define MAL_ESR_OTEI 0x00000004 113#define MAL_ESR_OSEI 0x00000002 114#define MAL_ESR_PBEI 0x00000001 115 /* ^^ ^^ */ 116 /* Mal IER */ 117#if defined(CONFIG_440SPE) || \ 118 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 119 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 120 defined(CONFIG_405EX) 121#define MAL_IER_PT 0x00000080 122#define MAL_IER_PRE 0x00000040 123#define MAL_IER_PWE 0x00000020 124#define MAL_IER_DE 0x00000010 125#define MAL_IER_OTE 0x00000004 126#define MAL_IER_OE 0x00000002 127#define MAL_IER_PE 0x00000001 128#else 129#define MAL_IER_DE 0x00000010 130#define MAL_IER_NE 0x00000008 131#define MAL_IER_TE 0x00000004 132#define MAL_IER_OPBE 0x00000002 133#define MAL_IER_PLBE 0x00000001 134#endif 135 136/* MAL Channel Active Set and Reset Registers */ 137#define MAL_TXRX_CASR (0x80000000) 138 139#define MAL_TXRX_CASR_V(__x) (__x) /* Channel 0 shifts 0, channel 1 shifts 1, etc */ 140 141 142/* MAL Buffer Descriptor structure */ 143typedef struct { 144 short ctrl; /* MAL / Commac status control bits */ 145 short data_len; /* Max length is 4K-1 (12 bits) */ 146 char *data_ptr; /* pointer to actual data buffer */ 147} mal_desc_t; 148 149#endif 150