LXR uboot/arch/x86/cpu/qemu/pci.c

   1/*
   2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <pci.h>
   9#include <pci_rom.h>
  10#include <asm/pci.h>
  11#include <asm/arch/device.h>
  12#include <asm/arch/qemu.h>
  13
  14DECLARE_GLOBAL_DATA_PTR;
  15
  16static bool i440fx;
  17
  18void board_pci_setup_hose(struct pci_controller *hose)
  19{
  20        hose->first_busno = 0;
  21        hose->last_busno = 0;
  22
  23        /* PCI memory space */
  24        pci_set_region(hose->regions + 0,
  25                       CONFIG_PCI_MEM_BUS,
  26                       CONFIG_PCI_MEM_PHYS,
  27                       CONFIG_PCI_MEM_SIZE,
  28                       PCI_REGION_MEM);
  29
  30        /* PCI IO space */
  31        pci_set_region(hose->regions + 1,
  32                       CONFIG_PCI_IO_BUS,
  33                       CONFIG_PCI_IO_PHYS,
  34                       CONFIG_PCI_IO_SIZE,
  35                       PCI_REGION_IO);
  36
  37        pci_set_region(hose->regions + 2,
  38                       CONFIG_PCI_PREF_BUS,
  39                       CONFIG_PCI_PREF_PHYS,
  40                       CONFIG_PCI_PREF_SIZE,
  41                       PCI_REGION_PREFETCH);
  42
  43        pci_set_region(hose->regions + 3,
  44                       0,
  45                       0,
  46                       gd->ram_size,
  47                       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  48
  49        hose->region_count = 4;
  50}
  51
  52int board_pci_post_scan(struct pci_controller *hose)
  53{
  54        int ret = 0;
  55        u16 device, xbcs;
  56        int pam, i;
  57        pci_dev_t vga;
  58        ulong start;
  59
  60        /*
  61         * i440FX and Q35 chipset have different PAM register offset, but with
  62         * the same bitfield layout. Here we determine the offset based on its
  63         * PCI device ID.
  64         */
  65        device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
  66        i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
  67        pam = i440fx ? I440FX_PAM : Q35_PAM;
  68
  69        /*
  70         * Initialize Programmable Attribute Map (PAM) Registers
  71         *
  72         * Configure legacy segments C/D/E/F to system RAM
  73         */
  74        for (i = 0; i < PAM_NUM; i++)
  75                x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
  76
  77        if (i440fx) {
  78                /*
  79                 * Enable legacy IDE I/O ports decode
  80                 *
  81                 * Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
  82                 * However Linux ata_piix driver does sanity check on these two
  83                 * registers to see whether legacy ports decode is turned on.
  84                 * This is to make Linux ata_piix driver happy.
  85                 */
  86                x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
  87                x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
  88
  89                /* Enable I/O APIC */
  90                xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
  91                xbcs |= APIC_EN;
  92                x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
  93        } else {
  94                /* Configure PCIe ECAM base address */
  95                x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
  96                                       CONFIG_PCIE_ECAM_BASE | BAR_EN);
  97        }
  98
  99        /*
 100         * QEMU emulated graphic card shows in the PCI configuration space with
 101         * PCI vendor id and device id as an artificial pair 0x1234:0x1111.
 102         * It is on PCI bus 0, function 0, but device number is not consistent
 103         * for the two x86 targets it supports. For i440FX and PIIX chipset
 104         * board, it shows as device 2, while for Q35 and ICH9 chipset board,
 105         * it shows as device 1.
 106         */
 107        vga = i440fx ? I440FX_VGA : Q35_VGA;
 108        start = get_timer(0);
 109        ret = pci_run_vga_bios(vga, NULL, PCI_ROM_USE_NATIVE);
 110        debug("BIOS ran in %lums\n", get_timer(start));
 111
 112        return ret;
 113}
 114
 115#ifdef CONFIG_GENERATE_MP_TABLE
 116int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
 117{
 118        u8 irq;
 119
 120        if (i440fx) {
 121                /*
 122                 * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
 123                 * connected to I/O APIC INTPIN#16-19. Instead they are routed
 124                 * to an irq number controled by the PIRQ routing register.
 125                 */
 126                irq = x86_pci_read_config8(PCI_BDF(bus, dev, func),
 127                                           PCI_INTERRUPT_LINE);
 128        } else {
 129                /*
 130                 * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
 131                 * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
 132                 */
 133                irq = pirq < 8 ? pirq + 16 : pirq + 12;
 134        }
 135
 136        return irq;
 137}
 138#endif
 139