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9#include <common.h>
10#include <hwconfig.h>
11#include <i2c.h>
12#include <asm/io.h>
13#include <asm/fsl_mpc83xx_serdes.h>
14#include <fdt_support.h>
15#include <spd_sdram.h>
16#include <vsc7385.h>
17#include <fsl_esdhc.h>
18
19#if defined(CONFIG_SYS_DRAM_TEST)
20int
21testdram(void)
22{
23 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
24 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
25 uint *p;
26
27 printf("Testing DRAM from 0x%08x to 0x%08x\n",
28 CONFIG_SYS_MEMTEST_START,
29 CONFIG_SYS_MEMTEST_END);
30
31 printf("DRAM test phase 1:\n");
32 for (p = pstart; p < pend; p++)
33 *p = 0xaaaaaaaa;
34
35 for (p = pstart; p < pend; p++) {
36 if (*p != 0xaaaaaaaa) {
37 printf("DRAM test fails at: %08x\n", (uint) p);
38 return 1;
39 }
40 }
41
42 printf("DRAM test phase 2:\n");
43 for (p = pstart; p < pend; p++)
44 *p = 0x55555555;
45
46 for (p = pstart; p < pend; p++) {
47 if (*p != 0x55555555) {
48 printf("DRAM test fails at: %08x\n", (uint) p);
49 return 1;
50 }
51 }
52
53 printf("DRAM test passed.\n");
54 return 0;
55}
56#endif
57
58#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
59void ddr_enable_ecc(unsigned int dram_size);
60#endif
61int fixed_sdram(void);
62
63phys_size_t initdram(int board_type)
64{
65 immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
66 u32 msize = 0;
67
68 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
69 return -1;
70
71#if defined(CONFIG_SPD_EEPROM)
72 msize = spd_sdram();
73#else
74 msize = fixed_sdram();
75#endif
76
77#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
78
79 ddr_enable_ecc(msize * 1024 * 1024);
80#endif
81
82 return (msize * 1024 * 1024);
83}
84
85#if !defined(CONFIG_SPD_EEPROM)
86
87
88
89int fixed_sdram(void)
90{
91 immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
92 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
93 u32 msize_log2 = __ilog2(msize);
94
95 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
96 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
97
98 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
99 udelay(50000);
100
101 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
102 udelay(1000);
103
104 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
105 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
106 udelay(1000);
107
108 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
109 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
110 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
111 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
112 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
113 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
114 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
115 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
116 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
117 sync();
118 udelay(1000);
119
120 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
121 udelay(2000);
122 return CONFIG_SYS_DDR_SIZE;
123}
124#endif
125
126int checkboard(void)
127{
128 puts("Board: Freescale MPC837xERDB\n");
129 return 0;
130}
131
132int board_early_init_f(void)
133{
134#ifdef CONFIG_FSL_SERDES
135 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
136 u32 spridr = in_be32(&immr->sysconf.spridr);
137
138
139 switch (PARTID_NO_E(spridr)) {
140 case SPR_8377:
141 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
142 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
143 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
144 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
145 break;
146 case SPR_8378:
147 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
148 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
149 break;
150 case SPR_8379:
151 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
152 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
153 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
154 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
155 break;
156 default:
157 printf("serdes not configured: unknown CPU part number: "
158 "%04x\n", spridr >> 16);
159 break;
160 }
161#endif
162 return 0;
163}
164
165#ifdef CONFIG_FSL_ESDHC
166int board_mmc_init(bd_t *bd)
167{
168 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
169 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
170 int esdhc_hwconfig_enabled = 0;
171
172 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
173 esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
174
175 if (esdhc_hwconfig_enabled == 0)
176 return 0;
177
178 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
179 clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
180
181 return fsl_esdhc_mmc_init(bd);
182}
183#endif
184
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186
187
188
189
190int misc_init_r(void)
191{
192 int rc = 0;
193
194#ifdef CONFIG_VSC7385_IMAGE
195 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
196 CONFIG_VSC7385_IMAGE_SIZE)) {
197 puts("Failure uploading VSC7385 microcode.\n");
198 rc = 1;
199 }
200#endif
201
202 return rc;
203}
204
205#if defined(CONFIG_OF_BOARD_SETUP)
206
207int ft_board_setup(void *blob, bd_t *bd)
208{
209#ifdef CONFIG_PCI
210 ft_pci_setup(blob, bd);
211#endif
212 ft_cpu_setup(blob, bd);
213 fdt_fixup_dr_usb(blob, bd);
214 fdt_fixup_esdhc(blob, bd);
215
216 return 0;
217}
218#endif
219
