LXR uboot/board/ifm/ac14xx/ac14xx.c

   1/*
   2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
   3 * (C) Copyright 2009 Dave Srl www.dave.eu
   4 * (C) Copyright 2010 ifm ecomatic GmbH
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#include <common.h>
  10#include <asm/bitops.h>
  11#include <command.h>
  12#include <asm/io.h>
  13#include <asm/processor.h>
  14#include <asm/mpc512x.h>
  15#include <fdt_support.h>
  16#ifdef CONFIG_MISC_INIT_R
  17#include <i2c.h>
  18#endif
  19
  20static int eeprom_diag;
  21static int mac_diag;
  22static int gpio_diag;
  23
  24DECLARE_GLOBAL_DATA_PTR;
  25
  26static void gpio_configure(void)
  27{
  28        immap_t *im;
  29        gpio512x_t *gpioregs;
  30
  31        im = (immap_t *) CONFIG_SYS_IMMR;
  32        gpioregs = &im->gpio;
  33        out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
  34        out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
  35
  36        /*
  37         * out_be32(&gpioregs->gpdir, 0xC2293020);
  38         * workaround for a hardware effect: configure direction in pieces,
  39         * setting all outputs at once drops the reset line too low and
  40         * makes us lose the MII connection (breaks ethernet for us)
  41         */
  42        out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
  43        setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
  44        udelay(10);
  45        setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
  46        udelay(10);
  47        setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
  48        udelay(10);
  49        setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
  50
  51        /* to turn from red to yellow when U-Boot runs */
  52        setbits_be32(&gpioregs->gpdat, 0x00002020);
  53        out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
  54        out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
  55        out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
  56        out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
  57}
  58
  59/* the physical location of the pins */
  60#define GPIOKEY_ROW_BITMASK     0x40000000
  61#define GPIOKEY_ROW_UPPER       0
  62#define GPIOKEY_ROW_LOWER       1
  63
  64#define GPIOKEY_COL0_BITMASK    0x20000000
  65#define GPIOKEY_COL1_BITMASK    0x10000000
  66#define GPIOKEY_COL2_BITMASK    0x08000000
  67
  68/* the logical presentation of pressed keys */
  69#define GPIOKEY_BIT_FNLEFT      (1 << 5)
  70#define GPIOKEY_BIT_FNRIGHT     (1 << 4)
  71#define GPIOKEY_BIT_DIRUP       (1 << 3)
  72#define GPIOKEY_BIT_DIRLEFT     (1 << 2)
  73#define GPIOKEY_BIT_DIRRIGHT    (1 << 1)
  74#define GPIOKEY_BIT_DIRDOWN     (1 << 0)
  75
  76/* the hotkey combination which starts recovery */
  77#define GPIOKEY_BITS_RECOVERY   (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
  78                                 GPIOKEY_BIT_DIRDOWN)
  79
  80static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
  81{
  82
  83        if (row)
  84                setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
  85        else
  86                clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
  87        udelay(10);
  88}
  89
  90static u32 gpio_querykbd(void)
  91{
  92        immap_t *im;
  93        gpio512x_t *gpioregs;
  94        u32 keybits;
  95        u32 input;
  96
  97        im = (immap_t *)CONFIG_SYS_IMMR;
  98        gpioregs = &im->gpio;
  99        keybits = 0;
 100
 101        /* query upper row */
 102        gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
 103        input = in_be32(&gpioregs->gpdat);
 104        if ((input & GPIOKEY_COL0_BITMASK) == 0)
 105                keybits |= GPIOKEY_BIT_FNLEFT;
 106        if ((input & GPIOKEY_COL1_BITMASK) == 0)
 107                keybits |= GPIOKEY_BIT_DIRUP;
 108        if ((input & GPIOKEY_COL2_BITMASK) == 0)
 109                keybits |= GPIOKEY_BIT_FNRIGHT;
 110
 111        /* query lower row */
 112        gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
 113        input = in_be32(&gpioregs->gpdat);
 114        if ((input & GPIOKEY_COL0_BITMASK) == 0)
 115                keybits |= GPIOKEY_BIT_DIRLEFT;
 116        if ((input & GPIOKEY_COL1_BITMASK) == 0)
 117                keybits |= GPIOKEY_BIT_DIRRIGHT;
 118        if ((input & GPIOKEY_COL2_BITMASK) == 0)
 119                keybits |= GPIOKEY_BIT_DIRDOWN;
 120
 121        /* return bit pattern for keys */
 122        return keybits;
 123}
 124
 125/* excerpt from the recovery's hw_info.h */
 126
 127struct __attribute__ ((__packed__)) eeprom_layout {
 128        char    magic[3];       /** 'ifm' */
 129        u8      len[2];         /** content length without magic/len fields */
 130        u8      version[3];     /** structure version */
 131        u8      type;           /** type of PCB */
 132        u8      reserved[0x37]; /** padding up to offset 0x40 */
 133        u8      macaddress[6];  /** ethernet MAC (for the mainboard) @0x40 */
 134};
 135
 136#define HW_COMP_MAINCPU 2
 137
 138static struct eeprom_layout eeprom_content;
 139static int eeprom_was_read;     /* has_been_read */
 140static int eeprom_is_valid;
 141static int eeprom_version;
 142
 143#define get_eeprom_field_int(name) ({ \
 144        int value; \
 145        int idx; \
 146        value = 0; \
 147        for (idx = 0; idx < sizeof(name); idx++) { \
 148                value <<= 8; \
 149                value |= name[idx]; \
 150        } \
 151        value; \
 152})
 153
 154static int read_eeprom(void)
 155{
 156        int eeprom_datalen;
 157        int ret;
 158
 159        if (eeprom_was_read)
 160                return 0;
 161
 162        eeprom_is_valid = 0;
 163        ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
 164                        CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
 165                        (uchar *)&eeprom_content, sizeof(eeprom_content));
 166        if (eeprom_diag) {
 167                printf("DIAG: %s() read rc[%d], size[%d]\n",
 168                        __func__, ret, sizeof(eeprom_content));
 169        }
 170
 171        if (ret != 0)
 172                return -1;
 173
 174        eeprom_was_read = 1;
 175
 176        /*
 177         * check validity of EEPROM content
 178         * (check version, length, optionally checksum)
 179         */
 180        eeprom_is_valid = 1;
 181        eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
 182        eeprom_version = get_eeprom_field_int(eeprom_content.version);
 183
 184        if (eeprom_diag) {
 185                printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
 186                        __func__, eeprom_content.magic[0],
 187                        eeprom_content.magic[1], eeprom_content.magic[2],
 188                        eeprom_datalen, eeprom_version, eeprom_content.type);
 189        }
 190        if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
 191                eeprom_is_valid = 0;
 192        if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
 193                eeprom_is_valid = 0;
 194        if ((eeprom_version != 1) && (eeprom_version != 2))
 195                eeprom_is_valid = 0;
 196        if (eeprom_content.type != HW_COMP_MAINCPU)
 197                eeprom_is_valid = 0;
 198
 199        if (eeprom_diag)
 200                printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
 201
 202        return ret;
 203}
 204
 205int mac_read_from_eeprom(void)
 206{
 207        const u8 *mac;
 208        const char *mac_txt;
 209
 210        if (read_eeprom()) {
 211                printf("I2C EEPROM read failed.\n");
 212                return -1;
 213        }
 214
 215        if (!eeprom_is_valid) {
 216                printf("I2C EEPROM content not valid\n");
 217                return -1;
 218        }
 219
 220        mac = NULL;
 221        switch (eeprom_version) {
 222        case 1:
 223        case 2:
 224                mac = (const u8 *)&eeprom_content.macaddress;
 225                break;
 226        }
 227
 228        if (mac && is_valid_ethaddr(mac)) {
 229                eth_setenv_enetaddr("ethaddr", mac);
 230                if (mac_diag) {
 231                        mac_txt = getenv("ethaddr");
 232                        if (mac_txt)
 233                                printf("DIAG: MAC value [%s]\n", mac_txt);
 234                        else
 235                                printf("DIAG: failed to setup MAC env\n");
 236                }
 237        }
 238
 239        return 0;
 240}
 241
 242/*
 243 * BEWARE!
 244 * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
 245 * which the ADS, Aria or PDM360NG boards are using
 246 * (the steps outlined here refer to the Micron datasheet)
 247 */
 248u32 sdram_init_seq[] = {
 249        /* item 6, at least one NOP after CKE went high */
 250        CONFIG_SYS_DDRCMD_NOP,
 251        CONFIG_SYS_DDRCMD_NOP,
 252        CONFIG_SYS_DDRCMD_NOP,
 253        CONFIG_SYS_DDRCMD_NOP,
 254        CONFIG_SYS_DDRCMD_NOP,
 255        CONFIG_SYS_DDRCMD_NOP,
 256        CONFIG_SYS_DDRCMD_NOP,
 257        CONFIG_SYS_DDRCMD_NOP,
 258        CONFIG_SYS_DDRCMD_NOP,
 259        CONFIG_SYS_DDRCMD_NOP,
 260        /* item 7, precharge all; item 8, tRP (20ns) */
 261        CONFIG_SYS_DDRCMD_PCHG_ALL,
 262        CONFIG_SYS_DDRCMD_NOP,
 263        /* item 9, extended mode register; item 10, tMRD 10ns) */
 264        CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
 265        CONFIG_SYS_DDRCMD_NOP,
 266        /*
 267         * item 11, (base) mode register _with_ reset DLL;
 268         * item 12, tMRD (10ns)
 269         */
 270        CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
 271        CONFIG_SYS_MICRON_BMODE_PARAM,
 272        CONFIG_SYS_DDRCMD_NOP,
 273        /* item 13, precharge all; item 14, tRP (20ns) */
 274        CONFIG_SYS_DDRCMD_PCHG_ALL,
 275        CONFIG_SYS_DDRCMD_NOP,
 276        /*
 277         * item 15, auto refresh (i.e. refresh with CKE held high);
 278         * item 16, tRFC (70ns)
 279         */
 280        CONFIG_SYS_DDRCMD_RFSH,
 281        CONFIG_SYS_DDRCMD_NOP,
 282        CONFIG_SYS_DDRCMD_NOP,
 283        CONFIG_SYS_DDRCMD_NOP,
 284        CONFIG_SYS_DDRCMD_NOP,
 285        CONFIG_SYS_DDRCMD_NOP,
 286        CONFIG_SYS_DDRCMD_NOP,
 287        CONFIG_SYS_DDRCMD_NOP,
 288        CONFIG_SYS_DDRCMD_NOP,
 289        /*
 290         * item 17, auto refresh (i.e. refresh with CKE held high);
 291         * item 18, tRFC (70ns)
 292         */
 293        CONFIG_SYS_DDRCMD_RFSH,
 294        CONFIG_SYS_DDRCMD_NOP,
 295        CONFIG_SYS_DDRCMD_NOP,
 296        CONFIG_SYS_DDRCMD_NOP,
 297        CONFIG_SYS_DDRCMD_NOP,
 298        CONFIG_SYS_DDRCMD_NOP,
 299        CONFIG_SYS_DDRCMD_NOP,
 300        CONFIG_SYS_DDRCMD_NOP,
 301        CONFIG_SYS_DDRCMD_NOP,
 302        /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
 303        CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
 304        CONFIG_SYS_DDRCMD_NOP,
 305        /*
 306         * item 21, "actually done", but make sure 200 DRAM clock cycles
 307         * have passed after DLL reset before READ requests are issued
 308         * (200 cycles at 160MHz -> 1.25 usec)
 309         */
 310        /* EMPTY, optional, we don't do it */
 311};
 312
 313phys_size_t initdram(int board_type)
 314{
 315        return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
 316}
 317
 318int misc_init_r(void)
 319{
 320        u32 keys;
 321        char *s;
 322        int want_recovery;
 323
 324        /* we use bus I2C-0 for the on-board eeprom */
 325        i2c_set_bus_num(0);
 326
 327        /* setup GPIO directions and initial values */
 328        gpio_configure();
 329
 330        /*
 331         * enforce the start of the recovery system when
 332         * - the appropriate keys were pressed
 333         * - "some" external software told us to
 334         * - a previous installation was aborted or has failed
 335         */
 336        want_recovery = 0;
 337        keys = gpio_querykbd();
 338        if (gpio_diag)
 339                printf("GPIO keyboard status [0x%02X]\n", keys);
 340        if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
 341                printf("detected recovery request (keyboard)\n");
 342                want_recovery = 1;
 343        }
 344        s = getenv("want_recovery");
 345        if ((s != NULL) && (*s != '\0')) {
 346                printf("detected recovery request (environment)\n");
 347                want_recovery = 1;
 348        }
 349        s = getenv("install_in_progress");
 350        if ((s != NULL) && (*s != '\0')) {
 351                printf("previous installation has not completed\n");
 352                want_recovery = 1;
 353        }
 354        s = getenv("install_failed");
 355        if ((s != NULL) && (*s != '\0')) {
 356                printf("previous installation has failed\n");
 357                want_recovery = 1;
 358        }
 359        if (want_recovery) {
 360                printf("enforced start of the recovery system\n");
 361                setenv("bootcmd", "run recovery");
 362        }
 363
 364        /*
 365         * boot the recovery system without waiting; boot the
 366         * production system without waiting by default, only
 367         * insert a pause (to provide a chance to get a prompt)
 368         * when GPIO keys were pressed during power on
 369         */
 370        if (want_recovery)
 371                setenv("bootdelay", "0");
 372        else if (!keys)
 373                setenv("bootdelay", "0");
 374        else
 375                setenv("bootdelay", "2");
 376
 377        /* get the ethernet MAC from I2C EEPROM */
 378        mac_read_from_eeprom();
 379
 380        return 0;
 381}
 382
 383/* setup specific IO pad configuration */
 384static  iopin_t ioregs_init[] = {
 385        {       /* LPC CS3 */
 386                offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
 387                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 388                IO_PIN_FMUX(1) | IO_PIN_DS(2),
 389        },
 390        {       /* LPC CS1 */
 391                offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
 392                IO_PIN_OVER_DRVSTR,
 393                IO_PIN_DS(2),
 394        },
 395        {       /* LPC CS2 */
 396                offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
 397                IO_PIN_OVER_DRVSTR,
 398                IO_PIN_DS(2),
 399        },
 400        {       /* LPC CS4, CS5 */
 401                offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
 402                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 403                IO_PIN_FMUX(1) | IO_PIN_DS(2),
 404        },
 405        {       /* SDHC CLK, CMD, D0, D1, D2, D3 */
 406                offsetof(struct ioctrl512x, io_control_pata_ior), 6,
 407                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 408                IO_PIN_FMUX(1) | IO_PIN_DS(2),
 409        },
 410        {       /* GPIO keyboard */
 411                offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
 412                IO_PIN_OVER_FMUX,
 413                IO_PIN_FMUX(3),
 414        },
 415        {       /* GPIO DN1 PF, LCD power, DN2 PF */
 416                offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
 417                IO_PIN_OVER_FMUX,
 418                IO_PIN_FMUX(3),
 419        },
 420        {       /* GPIO reset AS-i */
 421                offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
 422                IO_PIN_OVER_FMUX,
 423                IO_PIN_FMUX(3),
 424        },
 425        {       /* GPIO reset safety */
 426                offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
 427                IO_PIN_OVER_FMUX,
 428                IO_PIN_FMUX(3),
 429        },
 430        {       /* GPIO reset netX */
 431                offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
 432                IO_PIN_OVER_FMUX,
 433                IO_PIN_FMUX(3),
 434        },
 435        {       /* GPIO ma2 en */
 436                offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
 437                IO_PIN_OVER_FMUX,
 438                IO_PIN_FMUX(3),
 439        },
 440        {       /* GPIO SD CD, SD WP */
 441                offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
 442                IO_PIN_OVER_FMUX,
 443                IO_PIN_FMUX(3),
 444        },
 445        {       /* FEC RX DV */
 446                offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
 447                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 448                IO_PIN_FMUX(2) | IO_PIN_DS(2),
 449        },
 450        {       /* GPIO AS-i prog, AS-i done, LCD backlight */
 451                offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
 452                IO_PIN_OVER_FMUX,
 453                IO_PIN_FMUX(3),
 454        },
 455        {       /* GPIO AS-i wdg */
 456                offsetof(struct ioctrl512x, io_control_pci_req2), 1,
 457                IO_PIN_OVER_FMUX,
 458                IO_PIN_FMUX(3),
 459        },
 460        {       /* GPIO safety wdg */
 461                offsetof(struct ioctrl512x, io_control_pci_req1), 1,
 462                IO_PIN_OVER_FMUX,
 463                IO_PIN_FMUX(3),
 464        },
 465        {       /* GPIO netX wdg */
 466                offsetof(struct ioctrl512x, io_control_pci_req0), 1,
 467                IO_PIN_OVER_FMUX,
 468                IO_PIN_FMUX(3),
 469        },
 470        {       /* GPIO IRQ powerfail */
 471                offsetof(struct ioctrl512x, io_control_pci_inta), 1,
 472                IO_PIN_OVER_FMUX,
 473                IO_PIN_FMUX(3),
 474        },
 475        {       /* GPIO AS-i PWRD */
 476                offsetof(struct ioctrl512x, io_control_pci_frame), 1,
 477                IO_PIN_OVER_FMUX,
 478                IO_PIN_FMUX(3),
 479        },
 480        {       /* GPIO LED0, LED1 */
 481                offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
 482                IO_PIN_OVER_FMUX,
 483                IO_PIN_FMUX(3),
 484        },
 485        {       /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
 486                offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
 487                IO_PIN_OVER_FMUX,
 488                IO_PIN_FMUX(3),
 489        },
 490        {       /* DIU clk */
 491                offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
 492                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 493                IO_PIN_FMUX(2) | IO_PIN_DS(2),
 494        },
 495        {       /* FEC TX ER, CRS */
 496                offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
 497                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 498                IO_PIN_FMUX(1) | IO_PIN_DS(2),
 499        },
 500        {       /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
 501                offsetof(struct ioctrl512x, io_control_irq0), 1,
 502                IO_PIN_OVER_FMUX,
 503                IO_PIN_FMUX(3),
 504        },
 505        {       /*
 506                 * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
 507                 * rdx 3-0, mdio, rx clk
 508                 */
 509                offsetof(struct ioctrl512x, io_control_psc0_0), 15,
 510                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 511                IO_PIN_FMUX(1) | IO_PIN_DS(2),
 512        },
 513        /* optional: make sure PSC3 remains the serial console */
 514        {       /* LPC CS6 */
 515                offsetof(struct ioctrl512x, io_control_psc3_4), 1,
 516                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 517                IO_PIN_FMUX(1) | IO_PIN_DS(2),
 518        },
 519        /* make sure PSC4 remains available for SPI,
 520            *BUT* PSC4_1 is a GPIO kind of SS! */
 521        {       /* enforce drive strength on the SPI pin */
 522                offsetof(struct ioctrl512x, io_control_psc4_0), 5,
 523                IO_PIN_OVER_DRVSTR,
 524                IO_PIN_DS(2),
 525        },
 526        {
 527                offsetof(struct ioctrl512x, io_control_psc4_1), 1,
 528                IO_PIN_OVER_FMUX,
 529                IO_PIN_FMUX(3),
 530        },
 531        /* optional: make sure PSC5 remains available for SPI */
 532        {       /* enforce drive strength on the SPI pin */
 533                offsetof(struct ioctrl512x, io_control_psc5_0), 5,
 534                IO_PIN_OVER_DRVSTR,
 535                IO_PIN_DS(1),
 536        },
 537        {       /* LPC TSIZ1 */
 538                offsetof(struct ioctrl512x, io_control_psc6_0), 1,
 539                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 540                IO_PIN_FMUX(1) | IO_PIN_DS(2),
 541        },
 542        {       /* DIU hsync */
 543                offsetof(struct ioctrl512x, io_control_psc6_1), 1,
 544                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 545                IO_PIN_FMUX(2) | IO_PIN_DS(1),
 546        },
 547        {       /* DIU vsync */
 548                offsetof(struct ioctrl512x, io_control_psc6_4), 1,
 549                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 550                IO_PIN_FMUX(2) | IO_PIN_DS(1),
 551        },
 552        {       /* PSC7, part of DIU RGB */
 553                offsetof(struct ioctrl512x, io_control_psc7_0), 2,
 554                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 555                IO_PIN_FMUX(2) | IO_PIN_DS(1),
 556        },
 557        {       /* PSC7, safety UART */
 558                offsetof(struct ioctrl512x, io_control_psc7_2), 2,
 559                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 560                IO_PIN_FMUX(0) | IO_PIN_DS(1),
 561        },
 562        {       /* DIU (part of) RGB[] */
 563                offsetof(struct ioctrl512x, io_control_psc8_3), 16,
 564                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 565                IO_PIN_FMUX(2) | IO_PIN_DS(1),
 566        },
 567        {       /* DIU data enable */
 568                offsetof(struct ioctrl512x, io_control_psc11_4), 1,
 569                IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
 570                IO_PIN_FMUX(2) | IO_PIN_DS(1),
 571        },
 572        /* reduce LPB drive strength for improved EMI */
 573        {       /* LPC OE, LPC RW */
 574                offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
 575                IO_PIN_OVER_DRVSTR,
 576                IO_PIN_DS(2),
 577        },
 578        {       /* LPC AX03 through LPC AD00 */
 579                offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
 580                IO_PIN_OVER_DRVSTR,
 581                IO_PIN_DS(2),
 582        },
 583        {       /* LPC CS5 */
 584                offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
 585                IO_PIN_OVER_DRVSTR,
 586                IO_PIN_DS(2),
 587        },
 588        {       /* SDHC CLK */
 589                offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
 590                IO_PIN_OVER_DRVSTR,
 591                IO_PIN_DS(2),
 592        },
 593        {       /* SDHC DATA */
 594                offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
 595                IO_PIN_OVER_DRVSTR,
 596                IO_PIN_DS(2),
 597        },
 598};
 599
 600int checkboard(void)
 601{
 602        puts("Board: ifm AC14xx\n");
 603
 604        /* initialize function mux & slew rate IO inter alia on IO Pins  */
 605        iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
 606
 607        return 0;
 608}
 609
 610#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 611int ft_board_setup(void *blob, bd_t *bd)
 612{
 613        ft_cpu_setup(blob, bd);
 614
 615        return 0;
 616}
 617#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 618