LXR uboot/board/keymile/km83xx/km83xx.c

   1/*
   2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3 *                    Dave Liu <daveliu@freescale.com>
   4 *
   5 * Copyright (C) 2007 Logic Product Development, Inc.
   6 *                    Peter Barada <peterb@logicpd.com>
   7 *
   8 * Copyright (C) 2007 MontaVista Software, Inc.
   9 *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10 *
  11 * (C) Copyright 2008 - 2010
  12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13 *
  14 * SPDX-License-Identifier:     GPL-2.0+
  15 */
  16
  17#include <common.h>
  18#include <ioports.h>
  19#include <mpc83xx.h>
  20#include <i2c.h>
  21#include <miiphy.h>
  22#include <asm/io.h>
  23#include <asm/mmu.h>
  24#include <asm/processor.h>
  25#include <pci.h>
  26#include <libfdt.h>
  27#include <post.h>
  28
  29#include "../common/common.h"
  30
  31static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  32
  33const qe_iop_conf_t qe_iop_conf_tab[] = {
  34        /* port pin dir open_drain assign */
  35#if defined(CONFIG_MPC8360)
  36        /* MDIO */
  37        {0,  1, 3, 0, 2}, /* MDIO */
  38        {0,  2, 1, 0, 1}, /* MDC */
  39
  40        /* UCC4 - UEC */
  41        {1, 14, 1, 0, 1}, /* TxD0 */
  42        {1, 15, 1, 0, 1}, /* TxD1 */
  43        {1, 20, 2, 0, 1}, /* RxD0 */
  44        {1, 21, 2, 0, 1}, /* RxD1 */
  45        {1, 18, 1, 0, 1}, /* TX_EN */
  46        {1, 26, 2, 0, 1}, /* RX_DV */
  47        {1, 27, 2, 0, 1}, /* RX_ER */
  48        {1, 24, 2, 0, 1}, /* COL */
  49        {1, 25, 2, 0, 1}, /* CRS */
  50        {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
  51        {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
  52
  53        /* DUART - UART2 */
  54        {5,  0, 1, 0, 2}, /* UART2_SOUT */
  55        {5,  2, 1, 0, 1}, /* UART2_RTS */
  56        {5,  3, 2, 0, 2}, /* UART2_SIN */
  57        {5,  1, 2, 0, 3}, /* UART2_CTS */
  58#elif !defined(CONFIG_MPC8309)
  59        /* Local Bus */
  60        {0, 16, 1, 0, 3}, /* LA00 */
  61        {0, 17, 1, 0, 3}, /* LA01 */
  62        {0, 18, 1, 0, 3}, /* LA02 */
  63        {0, 19, 1, 0, 3}, /* LA03 */
  64        {0, 20, 1, 0, 3}, /* LA04 */
  65        {0, 21, 1, 0, 3}, /* LA05 */
  66        {0, 22, 1, 0, 3}, /* LA06 */
  67        {0, 23, 1, 0, 3}, /* LA07 */
  68        {0, 24, 1, 0, 3}, /* LA08 */
  69        {0, 25, 1, 0, 3}, /* LA09 */
  70        {0, 26, 1, 0, 3}, /* LA10 */
  71        {0, 27, 1, 0, 3}, /* LA11 */
  72        {0, 28, 1, 0, 3}, /* LA12 */
  73        {0, 29, 1, 0, 3}, /* LA13 */
  74        {0, 30, 1, 0, 3}, /* LA14 */
  75        {0, 31, 1, 0, 3}, /* LA15 */
  76
  77        /* MDIO */
  78        {3,  4, 3, 0, 2}, /* MDIO */
  79        {3,  5, 1, 0, 2}, /* MDC */
  80
  81        /* UCC4 - UEC */
  82        {1, 18, 1, 0, 1}, /* TxD0 */
  83        {1, 19, 1, 0, 1}, /* TxD1 */
  84        {1, 22, 2, 0, 1}, /* RxD0 */
  85        {1, 23, 2, 0, 1}, /* RxD1 */
  86        {1, 26, 2, 0, 1}, /* RxER */
  87        {1, 28, 2, 0, 1}, /* Rx_DV */
  88        {1, 30, 1, 0, 1}, /* TxEN */
  89        {1, 31, 2, 0, 1}, /* CRS */
  90        {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
  91#endif
  92
  93        /* END of table */
  94        {0,  0, 0, 0, QE_IOP_TAB_END},
  95};
  96
  97#if defined(CONFIG_SUVD3)
  98const uint upma_table[] = {
  99        0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
 100        0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
 101        0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
 102        0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
 103        0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
 104        0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
 105        0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
 106        0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
 107        0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
 108        0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
 109        0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
 110        0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
 111        0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
 112        0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
 113        0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
 114        0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01  /* Words 60 to 63 */
 115};
 116#endif
 117
 118static int piggy_present(void)
 119{
 120        struct km_bec_fpga __iomem *base =
 121                (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
 122
 123        return in_8(&base->bprth) & PIGGY_PRESENT;
 124}
 125
 126#if defined(CONFIG_KMVECT1)
 127int ethernet_present(void)
 128{
 129        /* ethernet port connected to simple switch without piggy */
 130        return 1;
 131}
 132#else
 133int ethernet_present(void)
 134{
 135        return piggy_present();
 136}
 137#endif
 138
 139
 140int board_early_init_r(void)
 141{
 142        struct km_bec_fpga *base =
 143                (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 144#if defined(CONFIG_SUVD3)
 145        immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 146        fsl_lbc_t *lbc = &immap->im_lbc;
 147        u32 *mxmr = &lbc->mamr;
 148#endif
 149
 150#if defined(CONFIG_MPC8360)
 151        unsigned short  svid;
 152        /*
 153         * Because of errata in the UCCs, we have to write to the reserved
 154         * registers to slow the clocks down.
 155         */
 156        svid =  SVR_REV(mfspr(SVR));
 157        switch (svid) {
 158        case 0x0020:
 159                /*
 160                 * MPC8360ECE.pdf QE_ENET10 table 4:
 161                 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
 162                 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
 163                 */
 164                setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
 165                break;
 166        case 0x0021:
 167                /*
 168                 * MPC8360ECE.pdf QE_ENET10 table 4:
 169                 * IMMR + 0x14AC[24:27] = 1010
 170                 */
 171                clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
 172                        0x00000050, 0x000000a0);
 173                break;
 174        }
 175#endif
 176
 177        /* enable the PHY on the PIGGY */
 178        setbits_8(&base->pgy_eth, 0x01);
 179        /* enable the Unit LED (green) */
 180        setbits_8(&base->oprth, WRL_BOOT);
 181        /* enable Application Buffer */
 182        setbits_8(&base->oprtl, OPRTL_XBUFENA);
 183
 184#if defined(CONFIG_SUVD3)
 185        /* configure UPMA for APP1 */
 186        upmconfig(UPMA, (uint *) upma_table,
 187                sizeof(upma_table) / sizeof(uint));
 188        out_be32(mxmr, CONFIG_SYS_MAMR);
 189#endif
 190        return 0;
 191}
 192
 193int misc_init_r(void)
 194{
 195        ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
 196        return 0;
 197}
 198
 199#if defined(CONFIG_KMVECT1)
 200#include <mv88e6352.h>
 201/* Marvell MV88E6122 switch configuration */
 202static struct mv88e_sw_reg extsw_conf[] = {
 203        /* port 1, FRONT_MDI, autoneg */
 204        { PORT(1), PORT_PHY, NO_SPEED_FOR },
 205        { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 206        { PHY(1), PHY_1000_CTRL, NO_ADV },
 207        { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN },
 208        { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
 209                FULL_DUPLEX },
 210        /* port 2, unused */
 211        { PORT(2), PORT_CTRL, PORT_DIS },
 212        { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
 213        { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
 214        /* port 3, BP_MII (CPU), PHY mode, 100BASE */
 215        { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 216        /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */
 217        { PORT(4), PORT_STATUS, NO_PHY_DETECT },
 218        { PORT(4), PORT_PHY, SPEED_1000_FOR },
 219        { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 220        /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */
 221        { PORT(5), PORT_STATUS, NO_PHY_DETECT },
 222        { PORT(5), PORT_PHY, SPEED_1000_FOR },
 223        { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 224        /*
 225         * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
 226         * acc . MV-S300889-00D.pdf , clause 4.5
 227         */
 228        { PORT(5), 0x1A, 0xADB1 },
 229        /* port 6, unused, this port has no phy */
 230        { PORT(6), PORT_CTRL, PORT_DIS },
 231        /*
 232         * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
 233         * acc . MV-S300889-00D.pdf , clause 4.5
 234         */
 235        { PORT(5), 0x1A, 0xADB1 },
 236};
 237#endif
 238
 239int last_stage_init(void)
 240{
 241#if defined(CONFIG_KMVECT1)
 242        struct km_bec_fpga __iomem *base =
 243                (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
 244        u8 tmp_reg;
 245
 246        /* Release mv88e6122 from reset */
 247        tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */
 248        out_8(&base->res1[0], tmp_reg);        /* GP28 as output */
 249        tmp_reg = in_8(&base->gprt3) | 0x10;   /* GP28 to high */
 250        out_8(&base->gprt3, tmp_reg);
 251
 252        /* configure MV88E6122 switch */
 253        char *name = "UEC2";
 254
 255        if (miiphy_set_current_dev(name))
 256                return 0;
 257
 258        mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
 259                ARRAY_SIZE(extsw_conf));
 260
 261        mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
 262
 263        if (piggy_present()) {
 264                setenv("ethact", "UEC2");
 265                setenv("netdev", "eth1");
 266                puts("using PIGGY for network boot\n");
 267        } else {
 268                setenv("netdev", "eth0");
 269                puts("using frontport for network boot\n");
 270        }
 271#endif
 272
 273#if defined(CONFIG_KMCOGE5NE)
 274        struct bfticu_iomap *base =
 275                (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
 276        u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
 277
 278        if (dip_switch != 0) {
 279                /* start bootloader */
 280                puts("DIP:   Enabled\n");
 281                setenv("actual_bank", "0");
 282        }
 283#endif
 284        set_km_env();
 285        return 0;
 286}
 287
 288static int fixed_sdram(void)
 289{
 290        immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 291        u32 msize = 0;
 292        u32 ddr_size;
 293        u32 ddr_size_log2;
 294
 295        out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
 296        out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
 297        out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
 298        out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
 299        out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
 300        out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
 301        out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
 302        out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
 303        out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
 304        out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
 305        out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
 306        out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
 307        out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
 308        udelay(200);
 309        setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
 310
 311        msize = CONFIG_SYS_DDR_SIZE << 20;
 312        disable_addr_trans();
 313        msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
 314        enable_addr_trans();
 315        msize /= (1024 * 1024);
 316        if (CONFIG_SYS_DDR_SIZE != msize) {
 317                for (ddr_size = msize << 20, ddr_size_log2 = 0;
 318                        (ddr_size > 1);
 319                        ddr_size = ddr_size >> 1, ddr_size_log2++)
 320                        if (ddr_size & 1)
 321                                return -1;
 322                out_be32(&im->sysconf.ddrlaw[0].ar,
 323                        (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
 324                out_be32(&im->ddr.csbnds[0].csbnds,
 325                        (((msize / 16) - 1) & 0xff));
 326        }
 327
 328        return msize;
 329}
 330
 331phys_size_t initdram(int board_type)
 332{
 333        immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 334        u32 msize = 0;
 335
 336        if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
 337                return -1;
 338
 339        out_be32(&im->sysconf.ddrlaw[0].bar,
 340                CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
 341        msize = fixed_sdram();
 342
 343#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 344        /*
 345         * Initialize DDR ECC byte
 346         */
 347        ddr_enable_ecc(msize * 1024 * 1024);
 348#endif
 349
 350        /* return total bus SDRAM size(bytes)  -- DDR */
 351        return msize * 1024 * 1024;
 352}
 353
 354int checkboard(void)
 355{
 356        puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
 357
 358        if (piggy_present())
 359                puts(" with PIGGY.");
 360        puts("\n");
 361        return 0;
 362}
 363
 364#if defined(CONFIG_OF_BOARD_SETUP)
 365int ft_board_setup(void *blob, bd_t *bd)
 366{
 367        ft_cpu_setup(blob, bd);
 368
 369        return 0;
 370}
 371#endif
 372
 373#if defined(CONFIG_HUSH_INIT_VAR)
 374int hush_init_var(void)
 375{
 376        ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
 377        return 0;
 378}
 379#endif
 380
 381#if defined(CONFIG_POST)
 382int post_hotkeys_pressed(void)
 383{
 384        int testpin = 0;
 385        struct km_bec_fpga *base =
 386                (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 387        int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
 388        testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
 389        debug("post_hotkeys_pressed: %d\n", !testpin);
 390        return testpin;
 391}
 392
 393ulong post_word_load(void)
 394{
 395        void* addr = (ulong *) (CPM_POST_WORD_ADDR);
 396        debug("post_word_load 0x%08lX:  0x%08X\n", (ulong)addr, in_le32(addr));
 397        return in_le32(addr);
 398
 399}
 400void post_word_store(ulong value)
 401{
 402        void* addr = (ulong *) (CPM_POST_WORD_ADDR);
 403        debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
 404        out_le32(addr, value);
 405}
 406
 407int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 408{
 409        *vstart = CONFIG_SYS_MEMTEST_START;
 410        *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
 411        debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
 412
 413        return 0;
 414}
 415#endif
 416