LXR uboot/board/renesas/sh7753evb/sh7753evb.c

   1/*
   2 * Copyright (C) 2012  Renesas Solutions Corp.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <malloc.h>
   9#include <asm/processor.h>
  10#include <asm/io.h>
  11#include <asm/mmc.h>
  12#include <spi.h>
  13#include <spi_flash.h>
  14
  15int checkboard(void)
  16{
  17        puts("BOARD: SH7753 EVB\n");
  18
  19        return 0;
  20}
  21
  22static void init_gpio(void)
  23{
  24        struct gpio_regs *gpio = GPIO_BASE;
  25        struct sermux_regs *sermux = SERMUX_BASE;
  26
  27        /* GPIO */
  28        writew(0x0000, &gpio->pacr);    /* GETHER */
  29        writew(0x0001, &gpio->pbcr);    /* INTC */
  30        writew(0x0000, &gpio->pccr);    /* PWMU, INTC */
  31        writew(0x0000, &gpio->pdcr);    /* SPI0 */
  32        writew(0xeaff, &gpio->pecr);    /* GPIO */
  33        writew(0x0000, &gpio->pfcr);    /* WDT */
  34        writew(0x0004, &gpio->pgcr);    /* SPI0, GETHER MDIO gate(PTG1) */
  35        writew(0x0000, &gpio->phcr);    /* SPI1 */
  36        writew(0x0000, &gpio->picr);    /* SDHI */
  37        writew(0x0000, &gpio->pjcr);    /* SCIF4 */
  38        writew(0x0003, &gpio->pkcr);    /* SerMux */
  39        writew(0x0000, &gpio->plcr);    /* SerMux */
  40        writew(0x0000, &gpio->pmcr);    /* RIIC */
  41        writew(0x0000, &gpio->pncr);    /* USB, SGPIO */
  42        writew(0x0000, &gpio->pocr);    /* SGPIO */
  43        writew(0xd555, &gpio->pqcr);    /* GPIO */
  44        writew(0x0000, &gpio->prcr);    /* RIIC */
  45        writew(0x0000, &gpio->pscr);    /* RIIC */
  46        writew(0x0000, &gpio->ptcr);    /* STATUS */
  47        writeb(0x00, &gpio->pudr);
  48        writew(0x5555, &gpio->pucr);    /* Debug LED */
  49        writew(0x0000, &gpio->pvcr);    /* RSPI */
  50        writew(0x0000, &gpio->pwcr);    /* EVC */
  51        writew(0x0000, &gpio->pxcr);    /* LBSC */
  52        writew(0x0000, &gpio->pycr);    /* LBSC */
  53        writew(0x0000, &gpio->pzcr);    /* eMMC */
  54        writew(0xfe00, &gpio->psel0);
  55        writew(0x0000, &gpio->psel1);
  56        writew(0x3000, &gpio->psel2);
  57        writew(0xff00, &gpio->psel3);
  58        writew(0x771f, &gpio->psel4);
  59        writew(0x0ffc, &gpio->psel5);
  60        writew(0x00ff, &gpio->psel6);
  61        writew(0xfc00, &gpio->psel7);
  62
  63        writeb(0x10, &sermux->smr0);    /* SMR0: SerMux mode 0 */
  64}
  65
  66static void init_usb_phy(void)
  67{
  68        struct usb_common_regs *common0 = USB0_COMMON_BASE;
  69        struct usb_common_regs *common1 = USB1_COMMON_BASE;
  70        struct usb0_phy_regs *phy = USB0_PHY_BASE;
  71        struct usb1_port_regs *port = USB1_PORT_BASE;
  72        struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
  73
  74        writew(0x0100, &phy->reset);            /* set reset */
  75        /* port0 = USB0, port1 = USB1 */
  76        writew(0x0002, &phy->portsel);
  77        writel(0x0001, &port->port1sel);        /* port1 = Host */
  78        writew(0x0111, &phy->reset);            /* clear reset */
  79
  80        writew(0x4000, &common0->suspmode);
  81        writew(0x4000, &common1->suspmode);
  82
  83#if defined(__LITTLE_ENDIAN)
  84        writel(0x00000000, &align->ehcidatac);
  85        writel(0x00000000, &align->ohcidatac);
  86#endif
  87}
  88
  89static void init_gether_mdio(void)
  90{
  91        struct gpio_regs *gpio = GPIO_BASE;
  92
  93        writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
  94        writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
  95}
  96
  97static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
  98{
  99        struct ether_mac_regs *ether;
 100        unsigned char mac[6];
 101        unsigned long val;
 102
 103        eth_parse_enetaddr(mac_string, mac);
 104
 105        if (!channel)
 106                ether = GETHER0_MAC_BASE;
 107        else
 108                ether = GETHER1_MAC_BASE;
 109
 110        val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
 111        writel(val, &ether->mahr);
 112        val = (mac[4] << 8) | mac[5];
 113        writel(val, &ether->malr);
 114}
 115
 116/*****************************************************************
 117 * This PMB must be set on this timing. The lowlevel_init is run on
 118 * Area 0(phys 0x00000000), so we have to map it.
 119 *
 120 * The new PMB table is following:
 121 * ent  virt            phys            v       sz      c       wt
 122 * 0    0xa0000000      0x40000000      1       128M    0       1
 123 * 1    0xa8000000      0x48000000      1       128M    0       1
 124 * 2    0xb0000000      0x50000000      1       128M    0       1
 125 * 3    0xb8000000      0x58000000      1       128M    0       1
 126 * 4    0x80000000      0x40000000      1       128M    1       1
 127 * 5    0x88000000      0x48000000      1       128M    1       1
 128 * 6    0x90000000      0x50000000      1       128M    1       1
 129 * 7    0x98000000      0x58000000      1       128M    1       1
 130 */
 131static void set_pmb_on_board_init(void)
 132{
 133        struct mmu_regs *mmu = MMU_BASE;
 134
 135        /* clear ITLB */
 136        writel(0x00000004, &mmu->mmucr);
 137
 138        /* delete PMB for SPIBOOT */
 139        writel(0, PMB_ADDR_BASE(0));
 140        writel(0, PMB_DATA_BASE(0));
 141
 142        /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
 143        /*                      ppn  ub v s1 s0  c  wt */
 144        writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
 145        writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
 146        writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
 147        writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
 148        writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
 149        writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
 150        writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
 151        writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
 152        writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
 153        writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
 154        writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
 155        writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
 156}
 157
 158int board_init(void)
 159{
 160        struct gether_control_regs *gether = GETHER_CONTROL_BASE;
 161
 162        init_gpio();
 163        set_pmb_on_board_init();
 164
 165        /* Sets TXnDLY to B'010 */
 166        writel(0x00000202, &gether->gbecont);
 167
 168        init_usb_phy();
 169        init_gether_mdio();
 170
 171        return 0;
 172}
 173
 174int dram_init(void)
 175{
 176        DECLARE_GLOBAL_DATA_PTR;
 177
 178        gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
 179        gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
 180        printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 181
 182        return 0;
 183}
 184
 185int board_mmc_init(bd_t *bis)
 186{
 187        struct gpio_regs *gpio = GPIO_BASE;
 188
 189        writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
 190        writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
 191        udelay(1);
 192        writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
 193        udelay(200);
 194
 195        return mmcif_mmc_init();
 196}
 197
 198static int get_sh_eth_mac_raw(unsigned char *buf, int size)
 199{
 200        struct spi_flash *spi;
 201        int ret;
 202
 203        spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
 204        if (spi == NULL) {
 205                printf("%s: spi_flash probe failed.\n", __func__);
 206                return 1;
 207        }
 208
 209        ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
 210        if (ret) {
 211                printf("%s: spi_flash read failed.\n", __func__);
 212                spi_flash_free(spi);
 213                return 1;
 214        }
 215        spi_flash_free(spi);
 216
 217        return 0;
 218}
 219
 220static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
 221{
 222        memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
 223                SH7753EVB_ETHERNET_MAC_SIZE);
 224        mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
 225
 226        return 0;
 227}
 228
 229static void init_ethernet_mac(void)
 230{
 231        char mac_string[64];
 232        char env_string[64];
 233        int i;
 234        unsigned char *buf;
 235
 236        buf = malloc(256);
 237        if (!buf) {
 238                printf("%s: malloc failed.\n", __func__);
 239                return;
 240        }
 241        get_sh_eth_mac_raw(buf, 256);
 242
 243        /* Gigabit Ethernet */
 244        for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
 245                get_sh_eth_mac(i, mac_string, buf);
 246                if (i == 0)
 247                        setenv("ethaddr", mac_string);
 248                else {
 249                        sprintf(env_string, "eth%daddr", i);
 250                        setenv(env_string, mac_string);
 251                }
 252                set_mac_to_sh_giga_eth_register(i, mac_string);
 253        }
 254
 255        free(buf);
 256}
 257
 258int board_late_init(void)
 259{
 260        init_ethernet_mac();
 261
 262        return 0;
 263}
 264
 265int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 266{
 267        int i, ret;
 268        char mac_string[256];
 269        struct spi_flash *spi;
 270        unsigned char *buf;
 271
 272        if (argc != 3) {
 273                buf = malloc(256);
 274                if (!buf) {
 275                        printf("%s: malloc failed.\n", __func__);
 276                        return 1;
 277                }
 278
 279                get_sh_eth_mac_raw(buf, 256);
 280
 281                /* print current MAC address */
 282                for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
 283                        get_sh_eth_mac(i, mac_string, buf);
 284                        printf("GETHERC ch%d = %s\n", i, mac_string);
 285                }
 286                free(buf);
 287                return 0;
 288        }
 289
 290        /* new setting */
 291        memset(mac_string, 0xff, sizeof(mac_string));
 292        sprintf(mac_string, "%s\t%s",
 293                argv[1], argv[2]);
 294
 295        /* write MAC data to SPI rom */
 296        spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
 297        if (!spi) {
 298                printf("%s: spi_flash probe failed.\n", __func__);
 299                return 1;
 300        }
 301
 302        ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
 303                                SH7753EVB_SPI_SECTOR_SIZE);
 304        if (ret) {
 305                printf("%s: spi_flash erase failed.\n", __func__);
 306                return 1;
 307        }
 308
 309        ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
 310                                sizeof(mac_string), mac_string);
 311        if (ret) {
 312                printf("%s: spi_flash write failed.\n", __func__);
 313                spi_flash_free(spi);
 314                return 1;
 315        }
 316        spi_flash_free(spi);
 317
 318        puts("The writing of the MAC address to SPI ROM was completed.\n");
 319
 320        return 0;
 321}
 322
 323U_BOOT_CMD(
 324        write_mac,      3,      1,      do_write_mac,
 325        "write MAC address for GETHERC",
 326        "[GETHERC ch0] [GETHERC ch1]\n"
 327);
 328