LXR uboot/drivers/pci/pci

   1/*
   2 * PCIe driver for Marvell MVEBU SoCs
   3 *
   4 * Based on Barebox drivers/pci/pci-mvebu.c
   5 *
   6 * Ported to U-Boot by:
   7 * Anton Schubert <anton.schubert@gmx.de>
   8 * Stefan Roese <sr@denx.de>
   9 *
  10 * SPDX-License-Identifier:     GPL-2.0
  11 */
  12
  13#include <common.h>
  14#include <pci.h>
  15#include <asm/errno.h>
  16#include <asm/io.h>
  17#include <asm/arch/cpu.h>
  18#include <asm/arch/soc.h>
  19#include <linux/mbus.h>
  20
  21DECLARE_GLOBAL_DATA_PTR;
  22
  23/* PCIe unit register offsets */
  24#define SELECT(x, n)                    ((x >> n) & 1UL)
  25
  26#define PCIE_DEV_ID_OFF                 0x0000
  27#define PCIE_CMD_OFF                    0x0004
  28#define PCIE_DEV_REV_OFF                0x0008
  29#define  PCIE_BAR_LO_OFF(n)             (0x0010 + ((n) << 3))
  30#define  PCIE_BAR_HI_OFF(n)             (0x0014 + ((n) << 3))
  31#define PCIE_CAPAB_OFF                  0x0060
  32#define PCIE_CTRL_STAT_OFF              0x0068
  33#define PCIE_HEADER_LOG_4_OFF           0x0128
  34#define  PCIE_BAR_CTRL_OFF(n)           (0x1804 + (((n) - 1) * 4))
  35#define  PCIE_WIN04_CTRL_OFF(n)         (0x1820 + ((n) << 4))
  36#define  PCIE_WIN04_BASE_OFF(n)         (0x1824 + ((n) << 4))
  37#define  PCIE_WIN04_REMAP_OFF(n)        (0x182c + ((n) << 4))
  38#define PCIE_WIN5_CTRL_OFF              0x1880
  39#define PCIE_WIN5_BASE_OFF              0x1884
  40#define PCIE_WIN5_REMAP_OFF             0x188c
  41#define PCIE_CONF_ADDR_OFF              0x18f8
  42#define  PCIE_CONF_ADDR_EN              BIT(31)
  43#define  PCIE_CONF_REG(r)               ((((r) & 0xf00) << 16) | ((r) & 0xfc))
  44#define  PCIE_CONF_BUS(b)               (((b) & 0xff) << 16)
  45#define  PCIE_CONF_DEV(d)               (((d) & 0x1f) << 11)
  46#define  PCIE_CONF_FUNC(f)              (((f) & 0x7) << 8)
  47#define  PCIE_CONF_ADDR(dev, reg) \
  48        (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev))    | \
  49         PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
  50         PCIE_CONF_ADDR_EN)
  51#define PCIE_CONF_DATA_OFF              0x18fc
  52#define PCIE_MASK_OFF                   0x1910
  53#define  PCIE_MASK_ENABLE_INTS          (0xf << 24)
  54#define PCIE_CTRL_OFF                   0x1a00
  55#define  PCIE_CTRL_X1_MODE              BIT(0)
  56#define PCIE_STAT_OFF                   0x1a04
  57#define  PCIE_STAT_BUS                  (0xff << 8)
  58#define  PCIE_STAT_DEV                  (0x1f << 16)
  59#define  PCIE_STAT_LINK_DOWN            BIT(0)
  60#define PCIE_DEBUG_CTRL                 0x1a60
  61#define  PCIE_DEBUG_SOFT_RESET          BIT(20)
  62
  63struct resource {
  64        u32 start;
  65        u32 end;
  66};
  67
  68struct mvebu_pcie {
  69        struct pci_controller hose;
  70        char *name;
  71        void __iomem *base;
  72        void __iomem *membase;
  73        struct resource mem;
  74        void __iomem *iobase;
  75        u32 port;
  76        u32 lane;
  77        u32 lane_mask;
  78        pci_dev_t dev;
  79};
  80
  81#define to_pcie(_hc)    container_of(_hc, struct mvebu_pcie, pci)
  82
  83/*
  84 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
  85 * into SoCs address space. Each controller will map 32M of MEM
  86 * and 64K of I/O space when registered.
  87 */
  88static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
  89#define PCIE_MEM_SIZE   (32 << 20)
  90
  91#if defined(CONFIG_ARMADA_38X)
  92#define PCIE_BASE(if)                                   \
  93        ((if) == 0 ?                                    \
  94         MVEBU_REG_PCIE_BASE + 0x40000 :                \
  95         MVEBU_REG_PCIE_BASE + 0x4000 * (if))
  96
  97/*
  98 * On A38x MV6820 these PEX ports are supported:
  99 *  0 - Port 0.0
 100 *  1 - Port 0.1
 101 *  2 - Port 0.2
 102 */
 103#define MAX_PEX 3
 104static struct mvebu_pcie pcie_bus[MAX_PEX];
 105
 106static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
 107                                int *mem_target, int *mem_attr)
 108{
 109        u8 port[] = { 0, 1, 2 };
 110        u8 lane[] = { 0, 0, 0 };
 111        u8 target[] = { 8, 4, 4 };
 112        u8 attr[] = { 0xe8, 0xe8, 0xd8 };
 113
 114        pcie->port = port[pex_idx];
 115        pcie->lane = lane[pex_idx];
 116        *mem_target = target[pex_idx];
 117        *mem_attr = attr[pex_idx];
 118}
 119#else
 120#define PCIE_BASE(if)                                                   \
 121        ((if) < 8 ?                                                     \
 122         (MVEBU_REG_PCIE_BASE + ((if) / 4) * 0x40000 + ((if) % 4) * 0x4000) : \
 123         (MVEBU_REG_PCIE_BASE + 0x2000 + ((if) % 8) * 0x40000))
 124
 125/*
 126 * On AXP MV78460 these PEX ports are supported:
 127 *  0 - Port 0.0
 128 *  1 - Port 0.1
 129 *  2 - Port 0.2
 130 *  3 - Port 0.3
 131 *  4 - Port 1.0
 132 *  5 - Port 1.1
 133 *  6 - Port 1.2
 134 *  7 - Port 1.3
 135 *  8 - Port 2.0
 136 *  9 - Port 3.0
 137 */
 138#define MAX_PEX 10
 139static struct mvebu_pcie pcie_bus[MAX_PEX];
 140
 141static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
 142                                int *mem_target, int *mem_attr)
 143{
 144        u8 port[] = { 0, 0, 0, 0, 1, 1, 1, 1, 2, 3 };
 145        u8 lane[] = { 0, 1, 2, 3, 0, 1, 2, 3, 0, 0 };
 146        u8 target[] = { 4, 4, 4, 4, 8, 8, 8, 8, 4, 8 };
 147        u8 attr[] = { 0xe8, 0xd8, 0xb8, 0x78,
 148                      0xe8, 0xd8, 0xb8, 0x78,
 149                      0xf8, 0xf8 };
 150
 151        pcie->port = port[pex_idx];
 152        pcie->lane = lane[pex_idx];
 153        *mem_target = target[pex_idx];
 154        *mem_attr = attr[pex_idx];
 155}
 156#endif
 157
 158static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
 159{
 160        u32 val;
 161        val = readl(pcie->base + PCIE_STAT_OFF);
 162        return !(val & PCIE_STAT_LINK_DOWN);
 163}
 164
 165static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
 166{
 167        u32 stat;
 168
 169        stat = readl(pcie->base + PCIE_STAT_OFF);
 170        stat &= ~PCIE_STAT_BUS;
 171        stat |= busno << 8;
 172        writel(stat, pcie->base + PCIE_STAT_OFF);
 173}
 174
 175static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
 176{
 177        u32 stat;
 178
 179        stat = readl(pcie->base + PCIE_STAT_OFF);
 180        stat &= ~PCIE_STAT_DEV;
 181        stat |= devno << 16;
 182        writel(stat, pcie->base + PCIE_STAT_OFF);
 183}
 184
 185static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
 186{
 187        u32 stat;
 188
 189        stat = readl(pcie->base + PCIE_STAT_OFF);
 190        return (stat & PCIE_STAT_BUS) >> 8;
 191}
 192
 193static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
 194{
 195        u32 stat;
 196
 197        stat = readl(pcie->base + PCIE_STAT_OFF);
 198        return (stat & PCIE_STAT_DEV) >> 16;
 199}
 200
 201static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
 202{
 203        return container_of(hose, struct mvebu_pcie, hose);
 204}
 205
 206static int mvebu_pcie_read_config_dword(struct pci_controller *hose,
 207                pci_dev_t dev, int offset, u32 *val)
 208{
 209        struct mvebu_pcie *pcie = hose_to_pcie(hose);
 210        int local_bus = PCI_BUS(pcie->dev);
 211        int local_dev = PCI_DEV(pcie->dev);
 212        u32 reg;
 213
 214        /* Only allow one other device besides the local one on the local bus */
 215        if (PCI_BUS(dev) == local_bus && PCI_DEV(dev) != local_dev) {
 216                if (local_dev == 0 && PCI_DEV(dev) != 1) {
 217                        /*
 218                         * If local dev is 0, the first other dev can
 219                         * only be 1
 220                         */
 221                        *val = 0xffffffff;
 222                        return 1;
 223                } else if (local_dev != 0 && PCI_DEV(dev) != 0) {
 224                        /*
 225                         * If local dev is not 0, the first other dev can
 226                         * only be 0
 227                         */
 228                        *val = 0xffffffff;
 229                        return 1;
 230                }
 231        }
 232
 233        /* write address */
 234        reg = PCIE_CONF_ADDR(dev, offset);
 235        writel(reg, pcie->base + PCIE_CONF_ADDR_OFF);
 236        *val = readl(pcie->base + PCIE_CONF_DATA_OFF);
 237
 238        return 0;
 239}
 240
 241static int mvebu_pcie_write_config_dword(struct pci_controller *hose,
 242                pci_dev_t dev, int offset, u32 val)
 243{
 244        struct mvebu_pcie *pcie = hose_to_pcie(hose);
 245        int local_bus = PCI_BUS(pcie->dev);
 246        int local_dev = PCI_DEV(pcie->dev);
 247
 248        /* Only allow one other device besides the local one on the local bus */
 249        if (PCI_BUS(dev) == local_bus && PCI_DEV(dev) != local_dev) {
 250                if (local_dev == 0 && PCI_DEV(dev) != 1) {
 251                        /*
 252                         * If local dev is 0, the first other dev can
 253                         * only be 1
 254                         */
 255                        return 1;
 256                } else if (local_dev != 0 && PCI_DEV(dev) != 0) {
 257                        /*
 258                         * If local dev is not 0, the first other dev can
 259                         * only be 0
 260                         */
 261                        return 1;
 262                }
 263        }
 264
 265        writel(PCIE_CONF_ADDR(dev, offset), pcie->base + PCIE_CONF_ADDR_OFF);
 266        writel(val, pcie->base + PCIE_CONF_DATA_OFF);
 267
 268        return 0;
 269}
 270
 271/*
 272 * Setup PCIE BARs and Address Decode Wins:
 273 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
 274 * WIN[0-3] -> DRAM bank[0-3]
 275 */
 276static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
 277{
 278        const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
 279        u32 size;
 280        int i;
 281
 282        /* First, disable and clear BARs and windows. */
 283        for (i = 1; i < 3; i++) {
 284                writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
 285                writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
 286                writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
 287        }
 288
 289        for (i = 0; i < 5; i++) {
 290                writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
 291                writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
 292                writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
 293        }
 294
 295        writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
 296        writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
 297        writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
 298
 299        /* Setup windows for DDR banks. Count total DDR size on the fly. */
 300        size = 0;
 301        for (i = 0; i < dram->num_cs; i++) {
 302                const struct mbus_dram_window *cs = dram->cs + i;
 303
 304                writel(cs->base & 0xffff0000,
 305                       pcie->base + PCIE_WIN04_BASE_OFF(i));
 306                writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
 307                writel(((cs->size - 1) & 0xffff0000) |
 308                       (cs->mbus_attr << 8) |
 309                       (dram->mbus_dram_target_id << 4) | 1,
 310                       pcie->base + PCIE_WIN04_CTRL_OFF(i));
 311
 312                size += cs->size;
 313        }
 314
 315        /* Round up 'size' to the nearest power of two. */
 316        if ((size & (size - 1)) != 0)
 317                size = 1 << fls(size);
 318
 319        /* Setup BAR[1] to all DRAM banks. */
 320        writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
 321        writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
 322        writel(((size - 1) & 0xffff0000) | 0x1,
 323               pcie->base + PCIE_BAR_CTRL_OFF(1));
 324}
 325
 326void pci_init_board(void)
 327{
 328        int mem_target, mem_attr, i;
 329        int bus = 0;
 330        u32 reg;
 331        u32 soc_ctrl = readl(MVEBU_SYSTEM_REG_BASE + 0x4);
 332
 333        /* Check SoC Control Power State */
 334        debug("%s: SoC Control %08x, 0en %01lx, 1en %01lx, 2en %01lx\n",
 335              __func__, soc_ctrl, SELECT(soc_ctrl, 0), SELECT(soc_ctrl, 1),
 336              SELECT(soc_ctrl, 2));
 337
 338        for (i = 0; i < MAX_PEX; i++) {
 339                struct mvebu_pcie *pcie = &pcie_bus[i];
 340                struct pci_controller *hose = &pcie->hose;
 341
 342                /* Get port number, lane number and memory target / attr */
 343                mvebu_get_port_lane(pcie, i, &mem_target, &mem_attr);
 344
 345                /* Don't read at all from pci registers if port power is down */
 346                if (pcie->lane == 0 && SELECT(soc_ctrl, pcie->port) == 0) {
 347                        i += 3;
 348                        debug("%s: skipping port %d\n", __func__, pcie->port);
 349                        continue;
 350                }
 351
 352                pcie->base = (void __iomem *)PCIE_BASE(i);
 353
 354                /* Check link and skip ports that have no link */
 355                if (!mvebu_pcie_link_up(pcie)) {
 356                        debug("%s: PCIe %d.%d - down\n", __func__,
 357                              pcie->port, pcie->lane);
 358                        continue;
 359                }
 360                debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
 361                      pcie->port, pcie->lane, (u32)pcie->base);
 362
 363                /* Read Id info and local bus/dev */
 364                debug("direct conf read %08x, local bus %d, local dev %d\n",
 365                      readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
 366                      mvebu_pcie_get_local_dev_nr(pcie));
 367
 368                mvebu_pcie_set_local_bus_nr(pcie, bus);
 369                mvebu_pcie_set_local_dev_nr(pcie, 0);
 370                pcie->dev = PCI_BDF(bus, 0, 0);
 371
 372                pcie->mem.start = (u32)mvebu_pcie_membase;
 373                pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
 374                mvebu_pcie_membase += PCIE_MEM_SIZE;
 375
 376                if (mvebu_mbus_add_window_by_id(mem_target, mem_attr,
 377                                                (phys_addr_t)pcie->mem.start,
 378                                                PCIE_MEM_SIZE)) {
 379                        printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
 380                               (u32)pcie->mem.start, PCIE_MEM_SIZE);
 381                }
 382
 383                /* Setup windows and configure host bridge */
 384                mvebu_pcie_setup_wins(pcie);
 385
 386                /* Master + slave enable. */
 387                reg = readl(pcie->base + PCIE_CMD_OFF);
 388                reg |= PCI_COMMAND_MEMORY;
 389                reg |= PCI_COMMAND_MASTER;
 390                reg |= BIT(10);         /* disable interrupts */
 391                writel(reg, pcie->base + PCIE_CMD_OFF);
 392
 393                /* Setup U-Boot PCI Controller */
 394                hose->first_busno = 0;
 395                hose->current_busno = bus;
 396
 397                /* PCI memory space */
 398                pci_set_region(hose->regions + 0, pcie->mem.start,
 399                               pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
 400                pci_set_region(hose->regions + 1,
 401                               0, 0,
 402                               gd->ram_size,
 403                               PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 404                hose->region_count = 2;
 405
 406                pci_set_ops(hose,
 407                            pci_hose_read_config_byte_via_dword,
 408                            pci_hose_read_config_word_via_dword,
 409                            mvebu_pcie_read_config_dword,
 410                            pci_hose_write_config_byte_via_dword,
 411                            pci_hose_write_config_word_via_dword,
 412                            mvebu_pcie_write_config_dword);
 413                pci_register_hose(hose);
 414
 415                hose->last_busno = pci_hose_scan(hose);
 416
 417                /* Set BAR0 to internal registers */
 418                writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
 419                writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
 420
 421                bus = hose->last_busno + 1;
 422        }
 423}
 424