1
2
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4
5
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10#define CONFIG_SYS_GENERIC_BOARD
11#define CONFIG_DISPLAY_BOARDINFO
12
13
14
15
16#define CONFIG_B4860QDS
17#define CONFIG_PHYS_64BIT
18
19#ifdef CONFIG_RAMBOOT_PBL
20#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
21#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
22#ifndef CONFIG_NAND
23#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
24#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
25#else
26#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
27#define CONFIG_SPL_ENV_SUPPORT
28#define CONFIG_SPL_SERIAL_SUPPORT
29#define CONFIG_SPL_FLUSH_IMAGE
30#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
31#define CONFIG_SPL_LIBGENERIC_SUPPORT
32#define CONFIG_SPL_LIBCOMMON_SUPPORT
33#define CONFIG_SPL_I2C_SUPPORT
34#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
35#define CONFIG_FSL_LAW
36#define CONFIG_SYS_TEXT_BASE 0x00201000
37#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
38#define CONFIG_SPL_PAD_TO 0x40000
39#define CONFIG_SPL_MAX_SIZE 0x28000
40#define RESET_VECTOR_OFFSET 0x27FFC
41#define BOOT_PAGE_OFFSET 0x27000
42#define CONFIG_SPL_NAND_SUPPORT
43#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
44#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
45#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
46#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
47#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
48#define CONFIG_SPL_NAND_BOOT
49#ifdef CONFIG_SPL_BUILD
50#define CONFIG_SPL_SKIP_RELOCATE
51#define CONFIG_SPL_COMMON_INIT_DDR
52#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
53#define CONFIG_SYS_NO_FLASH
54#endif
55#endif
56#endif
57
58#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
59
60#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
61#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
62 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
63#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
64#define CONFIG_SYS_NO_FLASH
65#endif
66
67
68#define CONFIG_BOOKE
69#define CONFIG_E500
70#define CONFIG_E500MC
71#define CONFIG_SYS_BOOK3E_HV
72#define CONFIG_MP
73
74#ifndef CONFIG_SYS_TEXT_BASE
75#define CONFIG_SYS_TEXT_BASE 0xeff40000
76#endif
77
78#ifndef CONFIG_RESET_VECTOR_ADDRESS
79#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
80#endif
81
82#define CONFIG_SYS_FSL_CPC
83#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
84#define CONFIG_FSL_IFC
85#define CONFIG_FSL_CAAM
86#define CONFIG_PCI
87#define CONFIG_PCIE1
88#define CONFIG_FSL_PCI_INIT
89#define CONFIG_SYS_PCI_64BIT
90
91#ifndef CONFIG_PPC_B4420
92#define CONFIG_SYS_SRIO
93#define CONFIG_SRIO1
94#define CONFIG_SRIO2
95#define CONFIG_SRIO_PCIE_BOOT_MASTER
96#endif
97
98#define CONFIG_FSL_LAW
99
100
101#define I2C_MUX_PCA_ADDR 0x77
102
103
104#define CONFIG_VSC_CROSSBAR
105#define I2C_CH_DEFAULT 0x8
106#define I2C_CH_VSC3316 0xc
107#define I2C_CH_VSC3308 0xd
108
109#define VSC3316_TX_ADDRESS 0x70
110#define VSC3316_RX_ADDRESS 0x71
111#define VSC3308_TX_ADDRESS 0x02
112#define VSC3308_RX_ADDRESS 0x03
113
114
115#define CONFIG_IDT8T49N222A
116#define I2C_CH_IDT 0x9
117
118#define IDT_SERDES1_ADDRESS 0x6E
119#define IDT_SERDES2_ADDRESS 0x6C
120
121
122#define I2C_MUX_CH_VOL_MONITOR 0xa
123#define I2C_VOL_MONITOR_ADDR 0x40
124#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
125#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
126#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
127
128#define CONFIG_ZM7300
129#define I2C_MUX_CH_DPM 0xa
130#define I2C_DPM_ADDR 0x28
131
132#define CONFIG_ENV_OVERWRITE
133
134#ifdef CONFIG_SYS_NO_FLASH
135#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
136#define CONFIG_ENV_IS_NOWHERE
137#endif
138#else
139#define CONFIG_FLASH_CFI_DRIVER
140#define CONFIG_SYS_FLASH_CFI
141#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
142#endif
143
144#if defined(CONFIG_SPIFLASH)
145#define CONFIG_SYS_EXTRA_ENV_RELOC
146#define CONFIG_ENV_IS_IN_SPI_FLASH
147#define CONFIG_ENV_SPI_BUS 0
148#define CONFIG_ENV_SPI_CS 0
149#define CONFIG_ENV_SPI_MAX_HZ 10000000
150#define CONFIG_ENV_SPI_MODE 0
151#define CONFIG_ENV_SIZE 0x2000
152#define CONFIG_ENV_OFFSET 0x100000
153#define CONFIG_ENV_SECT_SIZE 0x10000
154#elif defined(CONFIG_SDCARD)
155#define CONFIG_SYS_EXTRA_ENV_RELOC
156#define CONFIG_ENV_IS_IN_MMC
157#define CONFIG_SYS_MMC_ENV_DEV 0
158#define CONFIG_ENV_SIZE 0x2000
159#define CONFIG_ENV_OFFSET (512 * 1097)
160#elif defined(CONFIG_NAND)
161#define CONFIG_SYS_EXTRA_ENV_RELOC
162#define CONFIG_ENV_IS_IN_NAND
163#define CONFIG_ENV_SIZE 0x2000
164#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
165#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
166#define CONFIG_ENV_IS_IN_REMOTE
167#define CONFIG_ENV_ADDR 0xffe20000
168#define CONFIG_ENV_SIZE 0x2000
169#elif defined(CONFIG_ENV_IS_NOWHERE)
170#define CONFIG_ENV_SIZE 0x2000
171#else
172#define CONFIG_ENV_IS_IN_FLASH
173#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
174#define CONFIG_ENV_SIZE 0x2000
175#define CONFIG_ENV_SECT_SIZE 0x20000
176#endif
177
178#ifndef __ASSEMBLY__
179unsigned long get_board_sys_clk(void);
180unsigned long get_board_ddr_clk(void);
181#endif
182#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
183#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
184
185
186
187
188#define CONFIG_SYS_CACHE_STASHING
189#define CONFIG_BTB
190#define CONFIG_DDR_ECC
191#ifdef CONFIG_DDR_ECC
192#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
193#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
194#endif
195
196#define CONFIG_ENABLE_36BIT_PHYS
197
198#ifdef CONFIG_PHYS_64BIT
199#define CONFIG_ADDR_MAP
200#define CONFIG_SYS_NUM_ADDR_MAP 64
201#endif
202
203#if 0
204#define CONFIG_POST CONFIG_SYS_POST_MEMORY
205#endif
206#define CONFIG_SYS_MEMTEST_START 0x00200000
207#define CONFIG_SYS_MEMTEST_END 0x00400000
208#define CONFIG_SYS_ALT_MEMTEST
209#define CONFIG_PANIC_HANG
210
211
212
213
214#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
215#define CONFIG_SYS_L3_SIZE 256 << 10
216#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
217#ifdef CONFIG_NAND
218#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
219#endif
220#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
221#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
222#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
223#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
224
225#ifdef CONFIG_PHYS_64BIT
226#define CONFIG_SYS_DCSRBAR 0xf0000000
227#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
228#endif
229
230
231#define CONFIG_ID_EEPROM
232#define CONFIG_SYS_I2C_EEPROM_NXID
233#define CONFIG_SYS_EEPROM_BUS_NUM 0
234#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
235#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
236#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
237#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
238
239
240
241
242#define CONFIG_VERY_BIG_RAM
243#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
244#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
245
246
247#define CONFIG_DIMM_SLOTS_PER_CTLR 1
248#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
249
250#define CONFIG_DDR_SPD
251#define CONFIG_SYS_DDR_RAW_TIMING
252#define CONFIG_SYS_FSL_DDR3
253#ifndef CONFIG_SPL_BUILD
254#define CONFIG_FSL_DDR_INTERACTIVE
255#endif
256
257#define CONFIG_SYS_SPD_BUS_NUM 0
258#define SPD_EEPROM_ADDRESS1 0x51
259#define SPD_EEPROM_ADDRESS2 0x53
260
261#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
262#define CONFIG_SYS_SDRAM_SIZE 2048
263
264
265
266
267#define CONFIG_SYS_FLASH_BASE 0xe0000000
268#ifdef CONFIG_PHYS_64BIT
269#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
270#else
271#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
272#endif
273
274#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
275#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
276 + 0x8000000) | \
277 CSPR_PORT_SIZE_16 | \
278 CSPR_MSEL_NOR | \
279 CSPR_V)
280#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
281#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
282 CSPR_PORT_SIZE_16 | \
283 CSPR_MSEL_NOR | \
284 CSPR_V)
285#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
286
287#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
288#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
289 FTIM0_NOR_TEADC(0x04) | \
290 FTIM0_NOR_TEAHC(0x20))
291#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
292 FTIM1_NOR_TRAD_NOR(0x1A) |\
293 FTIM1_NOR_TSEQRAD_NOR(0x13))
294#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
295 FTIM2_NOR_TCH(0x0E) | \
296 FTIM2_NOR_TWPH(0x0E) | \
297 FTIM2_NOR_TWP(0x1c))
298#define CONFIG_SYS_NOR_FTIM3 0x0
299
300#define CONFIG_SYS_FLASH_QUIET_TEST
301#define CONFIG_FLASH_SHOW_PROGRESS 45
302
303#define CONFIG_SYS_MAX_FLASH_BANKS 2
304#define CONFIG_SYS_MAX_FLASH_SECT 1024
305#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
306#define CONFIG_SYS_FLASH_WRITE_TOUT 500
307
308#define CONFIG_SYS_FLASH_EMPTY_INFO
309#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
310 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
311
312#define CONFIG_FSL_QIXIS
313#define CONFIG_FSL_QIXIS_V2
314#define QIXIS_BASE 0xffdf0000
315#ifdef CONFIG_PHYS_64BIT
316#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
317#else
318#define QIXIS_BASE_PHYS QIXIS_BASE
319#endif
320#define QIXIS_LBMAP_SWITCH 0x01
321#define QIXIS_LBMAP_MASK 0x0f
322#define QIXIS_LBMAP_SHIFT 0
323#define QIXIS_LBMAP_DFLTBANK 0x00
324#define QIXIS_LBMAP_ALTBANK 0x02
325#define QIXIS_RST_CTL_RESET 0x31
326#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
327#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
328#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
329
330#define CONFIG_SYS_CSPR3_EXT (0xf)
331#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
332 | CSPR_PORT_SIZE_8 \
333 | CSPR_MSEL_GPCM \
334 | CSPR_V)
335#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
336#define CONFIG_SYS_CSOR3 0x0
337
338#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
339 FTIM0_GPCM_TEADC(0x0e) | \
340 FTIM0_GPCM_TEAHC(0x0e))
341#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
342 FTIM1_GPCM_TRAD(0x1f))
343#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
344 FTIM2_GPCM_TCH(0x8) | \
345 FTIM2_GPCM_TWP(0x1f))
346#define CONFIG_SYS_CS3_FTIM3 0x0
347
348
349#define CONFIG_NAND_FSL_IFC
350#define CONFIG_SYS_NAND_MAX_ECCPOS 256
351#define CONFIG_SYS_NAND_MAX_OOBFREE 2
352#define CONFIG_SYS_NAND_BASE 0xff800000
353#ifdef CONFIG_PHYS_64BIT
354#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
355#else
356#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
357#endif
358
359#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
360#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
361 | CSPR_PORT_SIZE_8 \
362 | CSPR_MSEL_NAND \
363 | CSPR_V)
364#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
365
366#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
367 | CSOR_NAND_ECC_DEC_EN \
368 | CSOR_NAND_ECC_MODE_4 \
369 | CSOR_NAND_RAL_3 \
370 | CSOR_NAND_PGS_2K \
371 | CSOR_NAND_SPRZ_64 \
372 | CSOR_NAND_PB(64))
373
374#define CONFIG_SYS_NAND_ONFI_DETECTION
375
376
377#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
378 FTIM0_NAND_TWP(0x18) | \
379 FTIM0_NAND_TWCHT(0x07) | \
380 FTIM0_NAND_TWH(0x0a))
381#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
382 FTIM1_NAND_TWBE(0x39) | \
383 FTIM1_NAND_TRR(0x0e) | \
384 FTIM1_NAND_TRP(0x18))
385#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
386 FTIM2_NAND_TREH(0x0a) | \
387 FTIM2_NAND_TWHRE(0x1e))
388#define CONFIG_SYS_NAND_FTIM3 0x0
389
390#define CONFIG_SYS_NAND_DDR_LAW 11
391
392#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
393#define CONFIG_SYS_MAX_NAND_DEVICE 1
394#define CONFIG_CMD_NAND
395
396#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
397
398#if defined(CONFIG_NAND)
399#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
400#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
401#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
402#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
403#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
404#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
405#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
406#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
407#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
408#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
409#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
410#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
411#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
412#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
413#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
414#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
415#else
416#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
417#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
418#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
419#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
420#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
421#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
422#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
423#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
424#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
425#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
426#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
427#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
428#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
429#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
430#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
431#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
432#endif
433#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
434#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
435#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
436#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
437#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
438#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
439#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
440#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
441
442#ifdef CONFIG_SPL_BUILD
443#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
444#else
445#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
446#endif
447
448#if defined(CONFIG_RAMBOOT_PBL)
449#define CONFIG_SYS_RAMBOOT
450#endif
451
452#define CONFIG_BOARD_EARLY_INIT_R
453#define CONFIG_MISC_INIT_R
454
455#define CONFIG_HWCONFIG
456
457
458#define CONFIG_L1_INIT_RAM
459#define CONFIG_SYS_INIT_RAM_LOCK
460#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
461#ifdef CONFIG_PHYS_64BIT
462#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
463#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
464
465#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
466 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
467 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
468#else
469#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000
470#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
471#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
472#endif
473#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
474
475#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
476 GENERATED_GBL_DATA_SIZE)
477#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
478
479#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
480#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
481
482
483
484
485
486#define CONFIG_CONS_INDEX 1
487#define CONFIG_SYS_NS16550
488#define CONFIG_SYS_NS16550_SERIAL
489#define CONFIG_SYS_NS16550_REG_SIZE 1
490#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
491
492#define CONFIG_SYS_BAUDRATE_TABLE \
493 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
494
495#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
496#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
497#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
498#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
499#ifndef CONFIG_SPL_BUILD
500#define CONFIG_SYS_CONSOLE_IS_IN_ENV
501#endif
502
503
504
505#define CONFIG_SYS_HUSH_PARSER
506#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
507
508
509#define CONFIG_OF_LIBFDT
510#define CONFIG_OF_BOARD_SETUP
511#define CONFIG_OF_STDOUT_VIA_ALIAS
512
513
514#define CONFIG_FIT
515#define CONFIG_FIT_VERBOSE
516
517
518#define CONFIG_SYS_I2C
519#define CONFIG_SYS_I2C_FSL
520#define CONFIG_SYS_FSL_I2C_SPEED 400000
521#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
522#define CONFIG_SYS_FSL_I2C2_SPEED 400000
523#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
524#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
525#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
526
527
528
529
530#define RTC
531#define CONFIG_RTC_DS3231 1
532#define CONFIG_SYS_I2C_RTC_ADDR 0x68
533
534
535
536
537#ifdef CONFIG_SYS_SRIO
538#ifdef CONFIG_SRIO1
539#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
540#ifdef CONFIG_PHYS_64BIT
541#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
542#else
543#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
544#endif
545#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000
546#endif
547
548#ifdef CONFIG_SRIO2
549#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
550#ifdef CONFIG_PHYS_64BIT
551#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
552#else
553#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
554#endif
555#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000
556#endif
557#endif
558
559
560
561
562
563#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
564#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
565#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
566#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
567
568
569
570
571#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
572#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
573#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
574
575
576#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
577#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
578
579
580
581
582#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
583#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
584#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
585 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
586#endif
587
588
589
590
591#define CONFIG_FSL_ESPI
592#define CONFIG_SPI_FLASH_SST
593#define CONFIG_CMD_SF
594#define CONFIG_SF_DEFAULT_SPEED 10000000
595#define CONFIG_SF_DEFAULT_MODE 0
596
597
598
599
600#ifdef CONFIG_PHYS_64BIT
601#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
602#else
603#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
604#endif
605
606
607
608
609
610
611
612#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
613#ifdef CONFIG_PHYS_64BIT
614#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
615#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
616#else
617#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
618#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
619#endif
620#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
621#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
622#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
623#ifdef CONFIG_PHYS_64BIT
624#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
625#else
626#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
627#endif
628#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
629
630
631#ifndef CONFIG_NOBQFMAN
632#define CONFIG_SYS_DPAA_QBMAN
633#define CONFIG_SYS_BMAN_NUM_PORTALS 25
634#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
635#ifdef CONFIG_PHYS_64BIT
636#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
637#else
638#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
639#endif
640#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
641#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
642#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
643#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
644#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
645#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
646 CONFIG_SYS_BMAN_CENA_SIZE)
647#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
648#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
649#define CONFIG_SYS_QMAN_NUM_PORTALS 25
650#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
651#ifdef CONFIG_PHYS_64BIT
652#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
653#else
654#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
655#endif
656#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
657#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
658#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
659#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
660#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
661#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
662 CONFIG_SYS_QMAN_CENA_SIZE)
663#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
664#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
665
666#define CONFIG_SYS_DPAA_FMAN
667
668#define CONFIG_SYS_DPAA_RMAN
669
670
671#if defined(CONFIG_SPIFLASH)
672
673
674
675
676#define CONFIG_SYS_QE_FW_IN_SPIFLASH
677#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
678#elif defined(CONFIG_SDCARD)
679
680
681
682
683
684#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
685#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
686#elif defined(CONFIG_NAND)
687#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
688#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
689#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
690
691
692
693
694
695
696
697#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
698#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
699#else
700#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
701#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
702#endif
703#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
704#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
705#endif
706
707#ifdef CONFIG_SYS_DPAA_FMAN
708#define CONFIG_FMAN_ENET
709#define CONFIG_PHYLIB_10G
710#define CONFIG_PHY_VITESSE
711#define CONFIG_PHY_TERANETICS
712#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
713#define SGMII_CARD_PORT2_PHY_ADDR 0x10
714#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
715#define SGMII_CARD_PORT4_PHY_ADDR 0x11
716#endif
717
718#ifdef CONFIG_PCI
719#define CONFIG_PCI_INDIRECT_BRIDGE
720#define CONFIG_PCI_PNP
721
722#define CONFIG_PCI_SCAN_SHOW
723#define CONFIG_DOS_PARTITION
724#endif
725
726#ifdef CONFIG_FMAN_ENET
727#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
728#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
729
730
731#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7
732#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6
733
734
735#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
736#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
737#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
738#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
739
740#define CONFIG_MII
741#define CONFIG_ETHPRIME "FM1@DTSEC1"
742#define CONFIG_PHY_GIGE
743#endif
744
745#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
746
747
748
749
750#define CONFIG_LOADS_ECHO
751#define CONFIG_SYS_LOADS_BAUD_CHANGE
752
753
754
755
756#define CONFIG_CMD_DATE
757#define CONFIG_CMD_DHCP
758#define CONFIG_CMD_EEPROM
759#define CONFIG_CMD_ELF
760#define CONFIG_CMD_ERRATA
761#define CONFIG_CMD_GREPENV
762#define CONFIG_CMD_IRQ
763#define CONFIG_CMD_I2C
764#define CONFIG_CMD_MII
765#define CONFIG_CMD_PING
766#define CONFIG_CMD_REGINFO
767
768#ifdef CONFIG_PCI
769#define CONFIG_CMD_PCI
770#endif
771
772
773#ifdef CONFIG_FSL_CAAM
774#define CONFIG_CMD_HASH
775#define CONFIG_SHA_HW_ACCEL
776#endif
777
778
779
780
781#define CONFIG_HAS_FSL_DR_USB
782
783#ifdef CONFIG_HAS_FSL_DR_USB
784#define CONFIG_USB_EHCI
785
786#ifdef CONFIG_USB_EHCI
787#define CONFIG_CMD_USB
788#define CONFIG_USB_STORAGE
789#define CONFIG_USB_EHCI_FSL
790#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
791#define CONFIG_CMD_EXT2
792#endif
793#endif
794
795
796
797
798#define CONFIG_SYS_LONGHELP
799#define CONFIG_CMDLINE_EDITING
800#define CONFIG_AUTO_COMPLETE
801#define CONFIG_SYS_LOAD_ADDR 0x2000000
802#ifdef CONFIG_CMD_KGDB
803#define CONFIG_SYS_CBSIZE 1024
804#else
805#define CONFIG_SYS_CBSIZE 256
806#endif
807#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
808#define CONFIG_SYS_MAXARGS 16
809#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
810
811
812
813
814
815
816#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
817#define CONFIG_SYS_BOOTM_LEN (64 << 20)
818
819#ifdef CONFIG_CMD_KGDB
820#define CONFIG_KGDB_BAUDRATE 230400
821#endif
822
823
824
825
826#define CONFIG_ROOTPATH "/opt/nfsroot"
827#define CONFIG_BOOTFILE "uImage"
828#define CONFIG_UBOOTPATH "u-boot.bin"
829
830
831#define CONFIG_LOADADDR 1000000
832
833#define CONFIG_BOOTDELAY 10
834
835#define CONFIG_BAUDRATE 115200
836
837#define __USB_PHY_TYPE ulpi
838
839#ifdef CONFIG_PPC_B4860
840#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
841 "bank_intlv=cs0_cs1;" \
842 "en_cpc:cpc2;"
843#else
844#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
845#endif
846
847#define CONFIG_EXTRA_ENV_SETTINGS \
848 HWCONFIG \
849 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
850 "netdev=eth0\0" \
851 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
852 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
853 "tftpflash=tftpboot $loadaddr $uboot && " \
854 "protect off $ubootaddr +$filesize && " \
855 "erase $ubootaddr +$filesize && " \
856 "cp.b $loadaddr $ubootaddr $filesize && " \
857 "protect on $ubootaddr +$filesize && " \
858 "cmp.b $loadaddr $ubootaddr $filesize\0" \
859 "consoledev=ttyS0\0" \
860 "ramdiskaddr=2000000\0" \
861 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
862 "fdtaddr=c00000\0" \
863 "fdtfile=b4860qds/b4860qds.dtb\0" \
864 "bdev=sda3\0"
865
866
867
868#define CONFIG_PROOF_POINTS \
869 "setenv bootargs root=/dev/$bdev rw " \
870 "console=$consoledev,$baudrate $othbootargs;" \
871 "cpu 1 release 0x29000000 - - -;" \
872 "cpu 2 release 0x29000000 - - -;" \
873 "cpu 3 release 0x29000000 - - -;" \
874 "cpu 4 release 0x29000000 - - -;" \
875 "cpu 5 release 0x29000000 - - -;" \
876 "cpu 6 release 0x29000000 - - -;" \
877 "cpu 7 release 0x29000000 - - -;" \
878 "go 0x29000000"
879
880#define CONFIG_HVBOOT \
881 "setenv bootargs config-addr=0x60000000; " \
882 "bootm 0x01000000 - 0x00f00000"
883
884#define CONFIG_ALU \
885 "setenv bootargs root=/dev/$bdev rw " \
886 "console=$consoledev,$baudrate $othbootargs;" \
887 "cpu 1 release 0x01000000 - - -;" \
888 "cpu 2 release 0x01000000 - - -;" \
889 "cpu 3 release 0x01000000 - - -;" \
890 "cpu 4 release 0x01000000 - - -;" \
891 "cpu 5 release 0x01000000 - - -;" \
892 "cpu 6 release 0x01000000 - - -;" \
893 "cpu 7 release 0x01000000 - - -;" \
894 "go 0x01000000"
895
896#define CONFIG_LINUX \
897 "setenv bootargs root=/dev/ram rw " \
898 "console=$consoledev,$baudrate $othbootargs;" \
899 "setenv ramdiskaddr 0x02000000;" \
900 "setenv fdtaddr 0x00c00000;" \
901 "setenv loadaddr 0x1000000;" \
902 "bootm $loadaddr $ramdiskaddr $fdtaddr"
903
904#define CONFIG_HDBOOT \
905 "setenv bootargs root=/dev/$bdev rw " \
906 "console=$consoledev,$baudrate $othbootargs;" \
907 "tftp $loadaddr $bootfile;" \
908 "tftp $fdtaddr $fdtfile;" \
909 "bootm $loadaddr - $fdtaddr"
910
911#define CONFIG_NFSBOOTCOMMAND \
912 "setenv bootargs root=/dev/nfs rw " \
913 "nfsroot=$serverip:$rootpath " \
914 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
915 "console=$consoledev,$baudrate $othbootargs;" \
916 "tftp $loadaddr $bootfile;" \
917 "tftp $fdtaddr $fdtfile;" \
918 "bootm $loadaddr - $fdtaddr"
919
920#define CONFIG_RAMBOOTCOMMAND \
921 "setenv bootargs root=/dev/ram rw " \
922 "console=$consoledev,$baudrate $othbootargs;" \
923 "tftp $ramdiskaddr $ramdiskfile;" \
924 "tftp $loadaddr $bootfile;" \
925 "tftp $fdtaddr $fdtfile;" \
926 "bootm $loadaddr $ramdiskaddr $fdtaddr"
927
928#define CONFIG_BOOTCOMMAND CONFIG_LINUX
929
930#include <asm/fsl_secure_boot.h>
931
932#ifdef CONFIG_SECURE_BOOT
933#define CONFIG_CMD_BLOB
934#endif
935
936#endif
937