1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29#ifdef CONFIG_36BIT
30#define CONFIG_PHYS_64BIT
31#endif
32
33#ifdef CONFIG_SDCARD
34#define CONFIG_RAMBOOT_SDCARD
35#endif
36
37#ifdef CONFIG_SPIFLASH
38#define CONFIG_RAMBOOT_SPIFLASH
39#endif
40
41
42#define CONFIG_BOOKE
43#define CONFIG_E500
44#define CONFIG_P1022
45#define CONFIG_CONTROLCENTERD
46#define CONFIG_MP
47
48#define CONFIG_SYS_GENERIC_BOARD
49
50#define CONFIG_SYS_NO_FLASH
51#define CONFIG_ENABLE_36BIT_PHYS
52#define CONFIG_FSL_LAW
53
54#ifdef CONFIG_TRAILBLAZER
55#define CONFIG_IDENT_STRING " controlcenterd trailblazer 0.01"
56#else
57#define CONFIG_IDENT_STRING " controlcenterd 0.01"
58#endif
59
60#ifdef CONFIG_PHYS_64BIT
61#define CONFIG_ADDR_MAP
62#define CONFIG_SYS_NUM_ADDR_MAP 16
63#endif
64
65#define CONFIG_L2_CACHE
66#define CONFIG_BTB
67
68#define CONFIG_SYS_CLK_FREQ 66666600
69#define CONFIG_DDR_CLK_FREQ 66666600
70
71#define CONFIG_SYS_RAMBOOT
72
73#ifdef CONFIG_TRAILBLAZER
74
75#define CONFIG_SYS_TEXT_BASE 0xf8fc0000
76#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
77#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
78
79
80
81
82#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
83#ifdef CONFIG_PHYS_64BIT
84#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
85#else
86#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
87#endif
88#define CONFIG_SYS_L2_SIZE (256 << 10)
89#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
90
91#else
92
93#define CONFIG_SYS_TEXT_BASE 0x11000000
94#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
95#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
96
97#endif
98
99#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
100#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117#define CONFIG_SYS_INIT_RAM_LOCK
118#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
119#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
120#define CONFIG_SYS_GBL_DATA_OFFSET \
121 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
122#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
123
124#ifdef CONFIG_TRAILBLAZER
125
126#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
127#else
128#define CONFIG_SYS_CCSRBAR 0xffe00000
129#endif
130#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
131#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
132
133
134
135
136
137#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
138#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
139#define CONFIG_SYS_SDRAM_SIZE 1024
140#define CONFIG_VERY_BIG_RAM
141
142#define CONFIG_SYS_FSL_DDR3
143#define CONFIG_NUM_DDR_CONTROLLERS 1
144#define CONFIG_DIMM_SLOTS_PER_CTLR 1
145#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
146
147#define CONFIG_SYS_MEMTEST_START 0x00000000
148#define CONFIG_SYS_MEMTEST_END 0x3fffffff
149
150#ifdef CONFIG_TRAILBLAZER
151#define CONFIG_SPD_EEPROM
152#define SPD_EEPROM_ADDRESS 0x52
153
154#endif
155
156
157
158
159#define CONFIG_FSL_ELBC
160
161#define CONFIG_SYS_ELBC_BASE 0xe0000000
162#ifdef CONFIG_PHYS_64BIT
163#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
164#else
165#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
166#endif
167
168#define CONFIG_UART_BR_PRELIM \
169 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
170#define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
171
172#define CONFIG_SYS_BR0_PRELIM 0
173#define CONFIG_SYS_OR0_PRELIM 0
174
175#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
176#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
177
178
179
180
181#define CONFIG_CONS_INDEX 2
182#define CONFIG_SYS_NS16550
183#define CONFIG_SYS_NS16550_SERIAL
184#define CONFIG_SYS_NS16550_REG_SIZE 1
185#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
186
187#define CONFIG_SYS_BAUDRATE_TABLE \
188 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
189
190#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
191#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
192
193
194
195
196#define CONFIG_SYS_I2C
197#define CONFIG_SYS_I2C_FSL
198#define CONFIG_SYS_FSL_I2C_SPEED 400000
199#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
200#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
201#define CONFIG_SYS_FSL_I2C2_SPEED 400000
202#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
203#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
204
205#ifndef CONFIG_TRAILBLAZER
206#define CONFIG_CMD_I2C
207#endif
208
209#define CONFIG_PCA9698
210
211#define CONFIG_CMD_EEPROM
212#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
213#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
214
215#ifndef CONFIG_TRAILBLAZER
216
217
218
219#define CONFIG_HARD_SPI
220#define CONFIG_FSL_ESPI
221
222#define CONFIG_SPI_FLASH_STMICRO
223
224#define CONFIG_CMD_SF
225#define CONFIG_SF_DEFAULT_SPEED 10000000
226#define CONFIG_SF_DEFAULT_MODE 0
227#endif
228
229#define CONFIG_SHA1
230
231
232
233
234#define CONFIG_MMC
235#define CONFIG_GENERIC_MMC
236#define CONFIG_CMD_MMC
237
238#define CONFIG_FSL_ESDHC
239#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
240
241
242#ifndef CONFIG_TRAILBLAZER
243
244
245
246
247#define CONFIG_FSL_DIU_FB
248#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
249#define CONFIG_VIDEO
250#define CONFIG_CFB_CONSOLE
251#define CONFIG_VGA_AS_SINGLE_DEVICE
252#define CONFIG_CMD_BMP
253
254
255
256
257
258#define CONFIG_PCI
259#define CONFIG_PCIE1
260#define CONFIG_PCI_INDIRECT_BRIDGE
261#define CONFIG_PCI_PNP
262#define CONFIG_PCI_SCAN_SHOW
263#define CONFIG_SYS_PCI_64BIT
264#define CONFIG_CMD_PCI
265
266#define CONFIG_FSL_PCI_INIT
267#define CONFIG_FSL_PCIE_RESET
268
269#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
270#ifdef CONFIG_PHYS_64BIT
271#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
272#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
273#else
274#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
275#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
276#endif
277#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
278#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
279#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
280#ifdef CONFIG_PHYS_64BIT
281#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
282#else
283#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
284#endif
285#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
286
287
288
289
290#define CONFIG_LIBATA
291#define CONFIG_LBA48
292#define CONFIG_CMD_SATA
293
294#define CONFIG_FSL_SATA
295#define CONFIG_SYS_SATA_MAX_DEVICE 2
296#define CONFIG_SATA1
297#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
298#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
299#define CONFIG_SATA2
300#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
301#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
302
303
304
305
306#define CONFIG_TSEC_ENET
307
308#define CONFIG_TSECV2
309
310#define CONFIG_MII
311#define CONFIG_TSEC1 1
312#define CONFIG_TSEC1_NAME "eTSEC1"
313#define CONFIG_TSEC2 1
314#define CONFIG_TSEC2_NAME "eTSEC2"
315
316#define TSEC1_PHY_ADDR 0
317#define TSEC2_PHY_ADDR 1
318
319#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
320#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
321
322#define TSEC1_PHYIDX 0
323#define TSEC2_PHYIDX 0
324
325#define CONFIG_ETHPRIME "eTSEC1"
326
327#define CONFIG_PHY_GIGE
328
329
330
331
332#define CONFIG_USB_EHCI
333#define CONFIG_CMD_USB
334#define CONFIG_USB_STORAGE
335
336#define CONFIG_HAS_FSL_DR_USB
337#define CONFIG_USB_EHCI_FSL
338#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
339
340#endif
341
342
343
344
345#if defined(CONFIG_TRAILBLAZER)
346#define CONFIG_ENV_IS_NOWHERE
347#define CONFIG_ENV_SIZE 0x2000
348#elif defined(CONFIG_RAMBOOT_SPIFLASH)
349#define CONFIG_ENV_IS_IN_SPI_FLASH
350#define CONFIG_ENV_SPI_BUS 0
351#define CONFIG_ENV_SPI_CS 0
352#define CONFIG_ENV_SPI_MAX_HZ 10000000
353#define CONFIG_ENV_SPI_MODE 0
354#define CONFIG_ENV_SIZE 0x2000
355#define CONFIG_ENV_OFFSET 0x100000
356#define CONFIG_ENV_SECT_SIZE 0x10000
357#elif defined(CONFIG_RAMBOOT_SDCARD)
358#define CONFIG_ENV_IS_IN_MMC
359#define CONFIG_FSL_FIXED_MMC_LOCATION
360#define CONFIG_ENV_SIZE 0x2000
361#define CONFIG_SYS_MMC_ENV_DEV 0
362#endif
363
364#define CONFIG_SYS_EXTRA_ENV_RELOC
365
366#define CONFIG_SYS_CONSOLE_IS_IN_ENV
367
368
369
370
371#ifndef CONFIG_TRAILBLAZER
372#define CONFIG_SYS_HUSH_PARSER
373#define CONFIG_SYS_LONGHELP
374#define CONFIG_CMDLINE_EDITING
375#define CONFIG_AUTO_COMPLETE
376#endif
377
378#define CONFIG_SYS_LOAD_ADDR 0x2000000
379#ifdef CONFIG_CMD_KGDB
380#define CONFIG_SYS_CBSIZE 1024
381#else
382#define CONFIG_SYS_CBSIZE 256
383#endif
384
385#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
386#define CONFIG_SYS_MAXARGS 16
387#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
388
389#ifndef CONFIG_TRAILBLAZER
390
391#define CONFIG_CMD_ELF
392#define CONFIG_CMD_ERRATA
393#define CONFIG_CMD_EXT2
394#define CONFIG_CMD_FAT
395#define CONFIG_CMD_IRQ
396#define CONFIG_CMD_MII
397#define CONFIG_CMD_PING
398#define CONFIG_CMD_REGINFO
399
400
401
402
403#define CONFIG_BOARD_EARLY_INIT_F
404#define CONFIG_BOARD_EARLY_INIT_R
405#define CONFIG_MISC_INIT_R
406#define CONFIG_LAST_STAGE_INIT
407
408
409
410
411#define CONFIG_OF_LIBFDT
412#define CONFIG_OF_BOARD_SETUP
413#define CONFIG_OF_STDOUT_VIA_ALIAS
414
415
416#define CONFIG_FIT
417#define CONFIG_FIT_VERBOSE
418
419#else
420
421#define CONFIG_BOARD_EARLY_INIT_F
422#define CONFIG_BOARD_EARLY_INIT_R
423#define CONFIG_LAST_STAGE_INIT
424
425#endif
426
427
428
429
430#define CONFIG_HW_WATCHDOG
431#define CONFIG_LOADS_ECHO
432#define CONFIG_SYS_LOADS_BAUD_CHANGE
433#define CONFIG_DOS_PARTITION
434
435
436
437
438
439
440#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
441#define CONFIG_SYS_BOOTM_LEN (64 << 20)
442
443
444
445
446
447#ifdef CONFIG_TRAILBLAZER
448
449#define CONFIG_BOOTDELAY 0
450#define CONFIG_BAUDRATE 115200
451
452#define CONFIG_EXTRA_ENV_SETTINGS \
453 "mp_holdoff=1\0"
454
455#else
456
457#define CONFIG_HOSTNAME controlcenterd
458#define CONFIG_ROOTPATH "/opt/nfsroot"
459#define CONFIG_BOOTFILE "uImage"
460#define CONFIG_UBOOTPATH u-boot.bin
461
462#define CONFIG_LOADADDR 1000000
463
464#define CONFIG_BOOTDELAY 10
465
466#define CONFIG_BAUDRATE 115200
467
468#define CONFIG_EXTRA_ENV_SETTINGS \
469 "netdev=eth0\0" \
470 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
471 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
472 "tftpflash=tftpboot $loadaddr $uboot && " \
473 "protect off $ubootaddr +$filesize && " \
474 "erase $ubootaddr +$filesize && " \
475 "cp.b $loadaddr $ubootaddr $filesize && " \
476 "protect on $ubootaddr +$filesize && " \
477 "cmp.b $loadaddr $ubootaddr $filesize\0" \
478 "consoledev=ttyS1\0" \
479 "ramdiskaddr=2000000\0" \
480 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
481 "fdtaddr=c00000\0" \
482 "fdtfile=controlcenterd.dtb\0" \
483 "bdev=sda3\0"
484
485
486#define CONFIG_NFSBOOTCOMMAND \
487 "setenv bootargs root=/dev/nfs rw " \
488 "nfsroot=$serverip:$rootpath " \
489 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
490 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
491 "tftp $loadaddr $bootfile;" \
492 "tftp $fdtaddr $fdtfile;" \
493 "bootm $loadaddr - $fdtaddr"
494
495#define CONFIG_RAMBOOTCOMMAND \
496 "setenv bootargs root=/dev/ram rw " \
497 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
498 "tftp $ramdiskaddr $ramdiskfile;" \
499 "tftp $loadaddr $bootfile;" \
500 "tftp $fdtaddr $fdtfile;" \
501 "bootm $loadaddr $ramdiskaddr $fdtaddr"
502
503#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
504
505#endif
506
507#endif
508