1/* 2 * Common configuration options for ifm camera boards 3 * 4 * (C) Copyright 2005 5 * Sebastien Cazaux, ifm electronic gmbh 6 * 7 * (C) Copyright 2012 8 * DENX Software Engineering, Anatolij Gustschin <agust@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13#ifndef __O2D_CONFIG_H 14#define __O2D_CONFIG_H 15 16/* 17 * High Level Configuration Options 18 */ 19#define CONFIG_MPC5200 20#define CONFIG_DISPLAY_BOARDINFO 21#define CONFIG_SYS_GENERIC_BOARD 22 23#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */ 24 25#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 26#if defined(CONFIG_CMD_KGDB) 27/* log base 2 of the above value */ 28#define CONFIG_SYS_CACHELINE_SHIFT 5 29#endif 30 31/* 32#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 33 CONFIG_SYS_POST_I2C) 34*/ 35 36#ifdef CONFIG_POST 37/* preserve space for the post_word at end of on-chip SRAM */ 38#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) 39#endif 40 41/* 42 * Serial console configuration 43 */ 44#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */ 45#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 46#define CONFIG_SYS_BAUDRATE_TABLE \ 47 { 9600, 19200, 38400, 57600, 115200, 230400 } 48 49/* 50 * PCI Mapping: 51 * 0x40000000 - 0x4fffffff - PCI Memory 52 * 0x50000000 - 0x50ffffff - PCI IO Space 53 */ 54#undef CONFIG_PCI 55#define CONFIG_PCI_PNP 1 56 57#define CONFIG_PCI_MEM_BUS 0x40000000 58#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 59#define CONFIG_PCI_MEM_SIZE 0x10000000 60 61#define CONFIG_PCI_IO_BUS 0x50000000 62#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 63#define CONFIG_PCI_IO_SIZE 0x01000000 64 65#define CONFIG_SYS_XLB_PIPELINING 1 66 67/* Partitions */ 68#define CONFIG_MAC_PARTITION 69#define CONFIG_DOS_PARTITION 70#define CONFIG_ISO_PARTITION 71 72#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 73 74#define CONFIG_SYS_ALT_MEMTEST /* Much more complex memory test */ 75 76/* 77 * Supported commands 78 */ 79#define CONFIG_CMD_EEPROM 80#define CONFIG_CMD_FAT 81#define CONFIG_CMD_I2C 82#define CONFIG_CMD_MII 83#define CONFIG_CMD_PING 84#define CONFIG_CMD_DHCP 85#ifdef CONFIG_PCI 86#define CONFIG_CMD_PCI 87#endif 88#ifdef CONFIG_POST 89#define CONFIG_CMD_DIAG 90#endif 91 92#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000) 93/* Boot low with 16 or 32 MB Flash */ 94#define CONFIG_SYS_LOWBOOT 1 95#elif (CONFIG_SYS_TEXT_BASE != 0x00100000) 96#error "CONFIG_SYS_TEXT_BASE value is invalid" 97#endif 98 99#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 100 101#define CONFIG_PREBOOT "run master" 102 103#undef CONFIG_BOOTARGS 104 105#if !defined(CONFIG_CONSOLE_DEV) 106#define CONFIG_CONSOLE_DEV "ttyPSC1" 107#endif 108 109/* 110 * Default environment for booting old and new kernel versions 111 */ 112#define CONFIG_IFM_DEFAULT_ENV_OLD \ 113 "flash_self_old=run ramargs addip addmem;" \ 114 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 115 "flash_nfs_old=run nfsargs addip addmem;" \ 116 "bootm ${kernel_addr}\0" \ 117 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ 118 "run nfsargs addip addmem;" \ 119 "bootm ${kernel_addr_r}\0" 120 121#define CONFIG_IFM_DEFAULT_ENV_NEW \ 122 "fdt_addr_r=900000\0" \ 123 "fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0" \ 124 "flash_self=run ramargs addip addtty addmisc;" \ 125 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 126 "flash_nfs=run nfsargs addip addtty addmisc;" \ 127 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 128 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 129 "tftp ${fdt_addr_r} ${fdt_file}; " \ 130 "run nfsargs addip addtty addmisc;" \ 131 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 132 133#define CONFIG_IFM_DEFAULT_ENV_SETTINGS \ 134 "IOpin=0x64\0" \ 135 "addip=setenv bootargs ${bootargs} " \ 136 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 137 ":${hostname}:${netdev}:off panic=1\0" \ 138 "addmem=setenv bootargs ${bootargs} ${memlimit}\0" \ 139 "addmisc=sete bootargs ${bootargs} ${miscargs}\0" \ 140 "addtty=sete bootargs ${bootargs} console=" \ 141 CONFIG_CONSOLE_DEV ",${baudrate}\0" \ 142 "bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \ 143 "kernel_addr_r=600000\0" \ 144 "initrd_high=0x03e00000\0" \ 145 "memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \ 146 "memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \ 147 "netdev=eth0\0" \ 148 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 149 "nfsroot=${serverip}:${rootpath}\0" \ 150 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 151 "linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\ 152 "progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \ 153 "cp.b ${fileaddr} ${linbot} ${filesize}\0" \ 154 "ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\ 155 "progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};" \ 156 "cp.b ${fileaddr} ${rambot} ${filesize}\0" \ 157 "jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0" \ 158 "progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};" \ 159 "cp.b ${fileaddr} ${jffbot} ${filesize}\0" \ 160 "rootpath=/opt/eldk/ppc_6xx\0" \ 161 "uboname=" CONFIG_BOARD_NAME \ 162 "/u-boot.bin_" CONFIG_BOARD_NAME "_act\0" \ 163 "progubo=tftp 200000 ${uboname};" \ 164 "protect off ${ubobot} ${ubotop};" \ 165 "erase ${ubobot} ${ubotop};" \ 166 "cp.b ${fileaddr} ${ubobot} ${filesize}\0" \ 167 "unlock=yes\0" \ 168 "post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \ 169 "setenv bootdelay 1;" \ 170 "crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" " \ 171 BOARD_POST_CRC32_END";" \ 172 "setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0" 173 174#define CONFIG_BOOTCOMMAND "run post" 175 176/* 177 * IPB Bus clocking configuration. 178 */ 179#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 180 181#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) 182/* 183 * PCI Bus clocking configuration 184 * 185 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if 186 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 187 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. 188 */ 189#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ 190#endif 191 192/* 193 * I2C configuration 194 */ 195#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 196#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ 197#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 198#define CONFIG_SYS_I2C_SLAVE 0x7F 199 200/* 201 * EEPROM configuration: 202 * 203 * O2DNT board is equiped with Ramtron FRAM device FM24CL16 204 * 16 Kib Ferroelectric Nonvolatile serial RAM memory 205 * organized as 2048 x 8 bits and addressable as eight I2C devices 206 * 0x50 ... 0x57 each 256 bytes in size 207 * 208 */ 209#define CONFIG_SYS_I2C_FRAM 210#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 211#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 212#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 213/* 214 * There is no write delay with FRAM, write operations are performed at bus 215 * speed. Thus, no status polling or write delay is needed. 216 */ 217 218/* 219 * Flash configuration 220 */ 221#define CONFIG_SYS_FLASH_CFI 1 222#define CONFIG_FLASH_CFI_DRIVER 1 223#define CONFIG_FLASH_16BIT 224#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 225#define CONFIG_SYS_FLASH_CFI_AMD_RESET 226#define CONFIG_SYS_FLASH_EMPTY_INFO 227 228#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 229#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 230#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Erase Timeout (in ms) */ 231#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (in ms) */ 232/* Timeout for Flash Clear Lock Bits (in ms) */ 233#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 234/* "Real" (hardware) sectors protection */ 235#define CONFIG_SYS_FLASH_PROTECTION 236 237/* 238 * Environment settings 239 */ 240#define CONFIG_ENV_IS_IN_FLASH 1 241#define CONFIG_ENV_SIZE 0x20000 242#define CONFIG_ENV_SECT_SIZE 0x20000 243#define CONFIG_ENV_OVERWRITE 1 244#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) 245 246/* 247 * Memory map 248 */ 249#define CONFIG_SYS_MBAR 0xF0000000 250#define CONFIG_SYS_SDRAM_BASE 0x00000000 251#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 252 253/* Use SRAM until RAM will be available */ 254#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 255#ifdef CONFIG_POST 256/* preserve space for the post_word at end of on-chip SRAM */ 257#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE 258#else 259/* End of used area in DPRAM */ 260#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE 261#endif 262 263#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ 264 GENERATED_GBL_DATA_SIZE) 265#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 266 267#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 268#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* 192 kB for Monitor */ 269#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */ 270#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial map for Linux */ 271 272#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 273#define CONFIG_SYS_RAMBOOT 1 274#endif 275 276/* 277 * Ethernet configuration 278 */ 279#define CONFIG_MPC5xxx_FEC 280#define CONFIG_MPC5xxx_FEC_MII100 281#define CONFIG_PHY_ADDR 0x00 282#define CONFIG_RESET_PHY_R 283 284/* 285 * GPIO configuration 286 */ 287#define CONFIG_SYS_GPIO_DATADIR 0x00000064 /* PSC1_2, PSC2_1,2 output */ 288#define CONFIG_SYS_GPIO_OPENDRAIN 0x00000000 /* No open drain */ 289#define CONFIG_SYS_GPIO_DATAVALUE 0x00000000 /* PSC1_1 to 1, rest to 0 */ 290#define CONFIG_SYS_GPIO_ENABLE 0x00000064 /* PSC1_2, PSC2_1,2 enable */ 291 292/* 293 * Miscellaneous configurable options 294 */ 295#define CONFIG_SYS_LONGHELP /* undef to save memory */ 296#define CONFIG_CMDLINE_EDITING 297#define CONFIG_SYS_HUSH_PARSER 298 299#if defined(CONFIG_CMD_KGDB) 300#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 301#else 302#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 303#endif 304/* Print Buffer Size */ 305#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 306 sizeof(CONFIG_SYS_PROMPT) + 16) 307/* max number of command args */ 308#define CONFIG_SYS_MAXARGS 16 309/* Boot Argument Buffer Size */ 310#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 311 312/* default load address */ 313#define CONFIG_SYS_LOAD_ADDR 0x100000 314 315/* decrementer freq: 1 ms ticks */ 316 317/* 318 * Various low-level settings 319 */ 320#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 321#define CONFIG_SYS_HID0_FINAL HID0_ICE 322 323#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 324#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 325#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 326#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 327 328#define CONFIG_BOARD_EARLY_INIT_R 329 330#define CONFIG_SYS_CS_BURST 0x00000000 331#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 332 333/* 334 * DT support 335 */ 336#define CONFIG_OF_LIBFDT 1 337#define CONFIG_OF_BOARD_SETUP 1 338 339#define OF_CPU "PowerPC,5200@0" 340#define OF_SOC "soc5200@f0000000" 341#define OF_TBCLK (bd->bi_busfreq / 4) 342 343#endif /* __O2D_CONFIG_H */ 344