1/* 2 * Common configuration settings for the TI OMAP3 EVM board. 3 * 4 * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __OMAP3_EVM_COMMON_H 10#define __OMAP3_EVM_COMMON_H 11 12/* 13 * High level configuration options 14 */ 15#define CONFIG_OMAP /* This is TI OMAP core */ 16#define CONFIG_OMAP_GPIO 17#define CONFIG_OMAP_COMMON 18#define CONFIG_SYS_GENERIC_BOARD 19/* Common ARM Erratas */ 20#define CONFIG_ARM_ERRATA_454179 21#define CONFIG_ARM_ERRATA_430973 22#define CONFIG_ARM_ERRATA_621766 23 24#define CONFIG_SDRC /* The chip has SDRC controller */ 25 26#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */ 27#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */ 28 29/* 30 * Clock related definitions 31 */ 32#define V_OSCK 26000000 /* Clock output from T2 */ 33#define V_SCLK (V_OSCK >> 1) 34 35/* 36 * OMAP3 has 12 GP timers, they can be driven by the system clock 37 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 38 * This rate is divided by a local divisor. 39 */ 40#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 41#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 42 43/* Size of environment - 128KB */ 44#define CONFIG_ENV_SIZE (128 << 10) 45 46/* Size of malloc pool */ 47#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 48 49/* 50 * Physical Memory Map 51 * Note 1: CS1 may or may not be populated 52 * Note 2: SDRAM size is expected to be at least 32MB 53 */ 54#define CONFIG_NR_DRAM_BANKS 2 55#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 56#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 57 58/* Limits for memtest */ 59#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 60#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 61 0x01F00000) /* 31MB */ 62 63/* Default load address */ 64#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) 65 66/* ----------------------------------------------------------------------------- 67 * Hardware drivers 68 * ----------------------------------------------------------------------------- 69 */ 70 71/* 72 * NS16550 Configuration 73 */ 74#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 75 76#define CONFIG_SYS_NS16550 77#define CONFIG_SYS_NS16550_SERIAL 78#define CONFIG_SYS_NS16550_REG_SIZE (-4) 79#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 80 81/* 82 * select serial console configuration 83 */ 84#define CONFIG_CONS_INDEX 1 85#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ 86#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 87#define CONFIG_BAUDRATE 115200 88#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 89 115200} 90 91/* 92 * I2C 93 */ 94#define CONFIG_SYS_I2C 95#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 96#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 97#define CONFIG_SYS_I2C_OMAP34XX 98 99/* 100 * PISMO support 101 */ 102/* Monitor at start of flash - Reserve 2 sectors */ 103#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 104 105#define CONFIG_SYS_MONITOR_LEN (256 << 10) 106 107/* Start location & size of environment */ 108#define ONENAND_ENV_OFFSET 0x260000 109#define SMNAND_ENV_OFFSET 0x260000 110 111#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 112 113/* 114 * NAND 115 */ 116/* Physical address to access NAND */ 117#define CONFIG_SYS_NAND_ADDR NAND_BASE 118 119/* Physical address to access NAND at CS0 */ 120#define CONFIG_SYS_NAND_BASE NAND_BASE 121 122/* Max number of NAND devices */ 123#define CONFIG_SYS_MAX_NAND_DEVICE 1 124#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 125/* Timeout values (in ticks) */ 126#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 127#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 128 129/* Flash banks JFFS2 should use */ 130#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 131 CONFIG_SYS_MAX_NAND_DEVICE) 132 133#define CONFIG_SYS_JFFS2_MEM_NAND 134#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 135#define CONFIG_SYS_JFFS2_NUM_BANKS 1 136 137#define CONFIG_JFFS2_NAND 138/* nand device jffs2 lives on */ 139#define CONFIG_JFFS2_DEV "nand0" 140/* Start of jffs2 partition */ 141#define CONFIG_JFFS2_PART_OFFSET 0x680000 142/* Size of jffs2 partition */ 143#define CONFIG_JFFS2_PART_SIZE 0xf980000 144 145/* 146 * USB 147 */ 148#ifdef CONFIG_USB_OMAP3 149 150#ifdef CONFIG_USB_MUSB_HCD 151#define CONFIG_CMD_USB 152 153#define CONFIG_USB_STORAGE 154#define CONGIG_CMD_STORAGE 155#define CONFIG_CMD_FAT 156 157#ifdef CONFIG_USB_KEYBOARD 158#define CONFIG_SYS_USB_EVENT_POLL 159#define CONFIG_PREBOOT "usb start" 160#endif /* CONFIG_USB_KEYBOARD */ 161 162#endif /* CONFIG_USB_MUSB_HCD */ 163 164#ifdef CONFIG_USB_MUSB_UDC 165/* USB device configuration */ 166#define CONFIG_USB_DEVICE 167#define CONFIG_USB_TTY 168#define CONFIG_SYS_CONSOLE_IS_IN_ENV 169 170/* Change these to suit your needs */ 171#define CONFIG_USBD_VENDORID 0x0451 172#define CONFIG_USBD_PRODUCTID 0x5678 173#define CONFIG_USBD_MANUFACTURER "Texas Instruments" 174#define CONFIG_USBD_PRODUCT_NAME "EVM" 175#endif /* CONFIG_USB_MUSB_UDC */ 176 177#endif /* CONFIG_USB_OMAP3 */ 178 179/* ---------------------------------------------------------------------------- 180 * U-boot features 181 * ---------------------------------------------------------------------------- 182 */ 183#define CONFIG_SYS_MAXARGS 16 /* max args for a command */ 184 185#define CONFIG_MISC_INIT_R 186 187#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 188#define CONFIG_SETUP_MEMORY_TAGS 189#define CONFIG_INITRD_TAG 190#define CONFIG_REVISION_TAG 191 192/* Size of Console IO buffer */ 193#define CONFIG_SYS_CBSIZE 512 194 195/* Size of print buffer */ 196#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 197 sizeof(CONFIG_SYS_PROMPT) + 16) 198 199/* Size of bootarg buffer */ 200#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 201 202#define CONFIG_BOOTFILE "uImage" 203 204/* 205 * NAND / OneNAND 206 */ 207#if defined(CONFIG_CMD_NAND) 208#define CONFIG_SYS_FLASH_BASE NAND_BASE 209 210#define CONFIG_NAND_OMAP_GPMC 211#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 212#elif defined(CONFIG_CMD_ONENAND) 213#define CONFIG_SYS_FLASH_BASE ONENAND_MAP 214#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 215#endif 216 217#if !defined(CONFIG_ENV_IS_NOWHERE) 218#if defined(CONFIG_CMD_NAND) 219#define CONFIG_ENV_IS_IN_NAND 220#elif defined(CONFIG_CMD_ONENAND) 221#define CONFIG_ENV_IS_IN_ONENAND 222#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET 223#endif 224#endif /* CONFIG_ENV_IS_NOWHERE */ 225 226#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 227 228#if defined(CONFIG_CMD_NET) 229 230/* Ethernet (SMSC9115 from SMSC9118 family) */ 231#define CONFIG_SMC911X 232#define CONFIG_SMC911X_32_BIT 233#define CONFIG_SMC911X_BASE 0x2C000000 234 235/* BOOTP fields */ 236#define CONFIG_BOOTP_SUBNETMASK 0x00000001 237#define CONFIG_BOOTP_GATEWAY 0x00000002 238#define CONFIG_BOOTP_HOSTNAME 0x00000004 239#define CONFIG_BOOTP_BOOTPATH 0x00000010 240 241#endif /* CONFIG_CMD_NET */ 242 243/* Support for relocation */ 244#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 245#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 246#define CONFIG_SYS_INIT_RAM_SIZE 0x800 247#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 248 CONFIG_SYS_INIT_RAM_SIZE - \ 249 GENERATED_GBL_DATA_SIZE) 250 251/* ----------------------------------------------------------------------------- 252 * Board specific 253 * ----------------------------------------------------------------------------- 254 */ 255#define CONFIG_SYS_NO_FLASH 256 257/* Uncomment to define the board revision statically */ 258/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */ 259 260#define CONFIG_SYS_CACHELINE_SIZE 64 261 262/* Defines for SPL */ 263#define CONFIG_SPL_FRAMEWORK 264#define CONFIG_SPL_TEXT_BASE 0x40200800 265#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 266 267#define CONFIG_SPL_BSS_START_ADDR 0x80000000 268#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 269 270#define CONFIG_SPL_BOARD_INIT 271#define CONFIG_SPL_LIBCOMMON_SUPPORT 272#define CONFIG_SPL_LIBDISK_SUPPORT 273#define CONFIG_SPL_I2C_SUPPORT 274#define CONFIG_SPL_LIBGENERIC_SUPPORT 275#define CONFIG_SPL_SERIAL_SUPPORT 276#define CONFIG_SPL_POWER_SUPPORT 277#define CONFIG_SPL_OMAP3_ID_NAND 278#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 279 280/* 281 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 282 * 64 bytes before this address should be set aside for u-boot.img's 283 * header. That is 0x800FFFC0--0x80100000 should not be used for any 284 * other needs. 285 */ 286#define CONFIG_SYS_TEXT_BASE 0x80100000 287#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 288#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 289 290#endif /* __OMAP3_EVM_COMMON_H */ 291