LXR uboot/arch/arm/include/asm/arch-stm32f4/stm32.h

   1/*
   2 * (C) Copyright 2011
   3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
   4 *
   5 * (C) Copyright 2015
   6 * Kamil Lulko, <kamil.lulko@gmail.com>
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11#ifndef _MACH_STM32_H_
  12#define _MACH_STM32_H_
  13
  14/*
  15 * Peripheral memory map
  16 */
  17#define STM32_SYSMEM_BASE       0x1FFF0000
  18#define STM32_PERIPH_BASE       0x40000000
  19#define STM32_APB1PERIPH_BASE   (STM32_PERIPH_BASE + 0x00000000)
  20#define STM32_APB2PERIPH_BASE   (STM32_PERIPH_BASE + 0x00010000)
  21#define STM32_AHB1PERIPH_BASE   (STM32_PERIPH_BASE + 0x00020000)
  22#define STM32_AHB2PERIPH_BASE   (STM32_PERIPH_BASE + 0x10000000)
  23
  24#define STM32_BUS_MASK          0xFFFF0000
  25
  26/*
  27 * Register maps
  28 */
  29struct stm32_u_id_regs {
  30        u32 u_id_low;
  31        u32 u_id_mid;
  32        u32 u_id_high;
  33};
  34
  35struct stm32_rcc_regs {
  36        u32 cr;         /* RCC clock control */
  37        u32 pllcfgr;    /* RCC PLL configuration */
  38        u32 cfgr;       /* RCC clock configuration */
  39        u32 cir;        /* RCC clock interrupt */
  40        u32 ahb1rstr;   /* RCC AHB1 peripheral reset */
  41        u32 ahb2rstr;   /* RCC AHB2 peripheral reset */
  42        u32 ahb3rstr;   /* RCC AHB3 peripheral reset */
  43        u32 rsv0;
  44        u32 apb1rstr;   /* RCC APB1 peripheral reset */
  45        u32 apb2rstr;   /* RCC APB2 peripheral reset */
  46        u32 rsv1[2];
  47        u32 ahb1enr;    /* RCC AHB1 peripheral clock enable */
  48        u32 ahb2enr;    /* RCC AHB2 peripheral clock enable */
  49        u32 ahb3enr;    /* RCC AHB3 peripheral clock enable */
  50        u32 rsv2;
  51        u32 apb1enr;    /* RCC APB1 peripheral clock enable */
  52        u32 apb2enr;    /* RCC APB2 peripheral clock enable */
  53        u32 rsv3[2];
  54        u32 ahb1lpenr;  /* RCC AHB1 periph clk enable in low pwr mode */
  55        u32 ahb2lpenr;  /* RCC AHB2 periph clk enable in low pwr mode */
  56        u32 ahb3lpenr;  /* RCC AHB3 periph clk enable in low pwr mode */
  57        u32 rsv4;
  58        u32 apb1lpenr;  /* RCC APB1 periph clk enable in low pwr mode */
  59        u32 apb2lpenr;  /* RCC APB2 periph clk enable in low pwr mode */
  60        u32 rsv5[2];
  61        u32 bdcr;       /* RCC Backup domain control */
  62        u32 csr;        /* RCC clock control & status */
  63        u32 rsv6[2];
  64        u32 sscgr;      /* RCC spread spectrum clock generation */
  65        u32 plli2scfgr; /* RCC PLLI2S configuration */
  66        u32 pllsaicfgr;
  67        u32 dckcfgr;
  68};
  69
  70struct stm32_pwr_regs {
  71        u32 cr;
  72        u32 csr;
  73};
  74
  75struct stm32_flash_regs {
  76        u32 acr;
  77        u32 key;
  78        u32 optkeyr;
  79        u32 sr;
  80        u32 cr;
  81        u32 optcr;
  82        u32 optcr1;
  83};
  84
  85/*
  86 * Registers access macros
  87 */
  88#define STM32_U_ID_BASE         (STM32_SYSMEM_BASE + 0x7A10)
  89#define STM32_U_ID              ((struct stm32_u_id_regs *)STM32_U_ID_BASE)
  90
  91#define STM32_RCC_BASE          (STM32_AHB1PERIPH_BASE + 0x3800)
  92#define STM32_RCC               ((struct stm32_rcc_regs *)STM32_RCC_BASE)
  93
  94#define STM32_PWR_BASE          (STM32_APB1PERIPH_BASE + 0x7000)
  95#define STM32_PWR               ((struct stm32_pwr_regs *)STM32_PWR_BASE)
  96
  97#define STM32_FLASH_BASE        (STM32_AHB1PERIPH_BASE + 0x3C00)
  98#define STM32_FLASH             ((struct stm32_flash_regs *)STM32_FLASH_BASE)
  99
 100#define STM32_FLASH_SR_BSY              (1 << 16)
 101
 102#define STM32_FLASH_CR_PG               (1 << 0)
 103#define STM32_FLASH_CR_SER              (1 << 1)
 104#define STM32_FLASH_CR_STRT             (1 << 16)
 105#define STM32_FLASH_CR_LOCK             (1 << 31)
 106#define STM32_FLASH_CR_SNB_OFFSET       3
 107#define STM32_FLASH_CR_SNB_MASK         (15 << STM32_FLASH_CR_SNB_OFFSET)
 108
 109/*
 110 * Peripheral base addresses
 111 */
 112#define STM32_USART1_BASE       (STM32_APB2PERIPH_BASE + 0x1000)
 113#define STM32_USART2_BASE       (STM32_APB1PERIPH_BASE + 0x4400)
 114#define STM32_USART3_BASE       (STM32_APB1PERIPH_BASE + 0x4800)
 115#define STM32_USART6_BASE       (STM32_APB2PERIPH_BASE + 0x1400)
 116
 117enum clock {
 118        CLOCK_CORE,
 119        CLOCK_AHB,
 120        CLOCK_APB1,
 121        CLOCK_APB2
 122};
 123
 124int configure_clocks(void);
 125unsigned long clock_get(enum clock clck);
 126
 127#endif /* _MACH_STM32_H_ */
 128