LXR uboot/arch/arm/include/asm/arch-sunxi/p2wi.h

   1/*
   2 * Sunxi platform Push-Push i2c register definition.
   3 *
   4 * (c) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
   5 * http://linux-sunxi.org
   6 *
   7 * (c)Copyright 2006-2013
   8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   9 * Berg Xing <bergxing@allwinnertech.com>
  10 * Tom Cubie <tangliang@allwinnertech.com>
  11 *
  12 * SPDX-License-Identifier:     GPL-2.0+
  13 */
  14
  15#ifndef _SUNXI_P2WI_H
  16#define _SUNXI_P2WI_H
  17
  18#include <linux/types.h>
  19
  20#define P2WI_CTRL_RESET (0x1 << 0)
  21#define P2WI_CTRL_IRQ_EN (0x1 << 1)
  22#define P2WI_CTRL_TRANS_ABORT (0x1 << 6)
  23#define P2WI_CTRL_TRANS_START (0x1 << 7)
  24
  25#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0)
  26#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff)
  27#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1)
  28#define P2WI_CC_CLK_DIV(n) \
  29        __P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n))
  30#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8)
  31#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7)
  32
  33#define P2WI_IRQ_TRANS_DONE (0x1 << 0)
  34#define P2WI_IRQ_TRANS_ERR (0x1 << 1)
  35#define P2WI_IRQ_LOAD_BUSY (0x1 << 2)
  36
  37#define P2WI_STAT_TRANS_DONE (0x1 << 0)
  38#define P2WI_STAT_TRANS_ERR (0x1 << 1)
  39#define P2WI_STAT_LOAD_BUSY (0x1 << 2)
  40#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8)
  41#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff)
  42#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01
  43#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02
  44#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04
  45#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08
  46#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10
  47#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20
  48#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40
  49#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80
  50#define P2WI_STAT_TRANS_ERR_BYTE_1 \
  51        __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1)
  52#define P2WI_STAT_TRANS_ERR_BYTE_2 \
  53        __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2)
  54#define P2WI_STAT_TRANS_ERR_BYTE_3 \
  55        __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3)
  56#define P2WI_STAT_TRANS_ERR_BYTE_4 \
  57        __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4)
  58#define P2WI_STAT_TRANS_ERR_BYTE_5 \
  59        __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5)
  60#define P2WI_STAT_TRANS_ERR_BYTE_6 \
  61        __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6)
  62#define P2WI_STAT_TRANS_ERR_BYTE_7 \
  63        __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7)
  64#define P2WI_STAT_TRANS_ERR_BYTE_8 \
  65        __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8)
  66
  67#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0)
  68#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff)
  69#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8)
  70#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff)
  71#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16)
  72#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff)
  73#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24)
  74#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff)
  75#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0)
  76#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff)
  77#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8)
  78#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff)
  79#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16)
  80#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff)
  81#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24)
  82#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff)
  83
  84#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0)
  85#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7)
  86#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1)
  87#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4)
  88
  89#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0)
  90#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff)
  91#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8)
  92#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff)
  93#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16)
  94#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff)
  95#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24)
  96#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff)
  97#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0)
  98#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff)
  99#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8)
 100#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff)
 101#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16)
 102#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff)
 103#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24)
 104#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff)
 105
 106#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0)
 107#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1)
 108#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2)
 109#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3)
 110#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4)
 111#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5)
 112
 113#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0)
 114#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff)
 115#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8)
 116#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff)
 117#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16)
 118#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff)
 119#define P2WI_PM_INIT_SEND (0x1 << 31)
 120
 121struct sunxi_p2wi_reg {
 122        u32 ctrl;       /* 0x00 control */
 123        u32 cc;         /* 0x04 clock control */
 124        u32 irq;        /* 0x08 interrupt */
 125        u32 status;     /* 0x0c status */
 126        u32 dataddr0;   /* 0x10 data address 0 */
 127        u32 dataddr1;   /* 0x14 data address 1 */
 128        u32 numbytes;   /* 0x18 num bytes */
 129        u32 data0;      /* 0x1c data buffer 0 */
 130        u32 data1;      /* 0x20 data buffer 1 */
 131        u32 linectrl;   /* 0x24 line control */
 132        u32 pm;         /* 0x28 power management */
 133};
 134
 135void p2wi_init(void);
 136int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data);
 137int p2wi_read(const u8 addr, u8 *data);
 138int p2wi_write(const u8 addr, u8 data);
 139
 140#endif /* _SUNXI_P2WI_H */
 141