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14#ifndef AT91_PIO_H
15#define AT91_PIO_H
16
17
18#define AT91_ASM_PIO_RANGE 0x200
19#define AT91_ASM_PIOC_ASR \
20 (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
21#define AT91_ASM_PIOC_BSR \
22 (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
23#define AT91_ASM_PIOC_PDR \
24 (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
25#define AT91_ASM_PIOC_PUDR \
26 (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
27
28#define AT91_ASM_PIOD_PDR \
29 (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
30#define AT91_ASM_PIOD_PUDR \
31 (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
32#define AT91_ASM_PIOD_ASR \
33 (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
34
35#ifndef __ASSEMBLY__
36
37typedef struct at91_port {
38 u32 per;
39 u32 pdr;
40 u32 psr;
41 u32 reserved0;
42 u32 oer;
43 u32 odr;
44 u32 osr;
45 u32 reserved1;
46 u32 ifer;
47 u32 ifdr;
48 u32 ifsr;
49 u32 reserved2;
50 u32 sodr;
51 u32 codr;
52 u32 odsr;
53 u32 pdsr;
54 u32 ier;
55 u32 idr;
56 u32 imr;
57 u32 isr;
58 u32 mder;
59 u32 mddr;
60 u32 mdsr;
61 u32 reserved3;
62 u32 pudr;
63 u32 puer;
64 u32 pusr;
65 u32 reserved4;
66#if defined(CPU_HAS_PIO3)
67 u32 abcdsr1;
68 u32 abcdsr2;
69 u32 reserved5[2];
70 u32 ifscdr;
71 u32 ifscer;
72 u32 ifscsr;
73 u32 scdr;
74 u32 ppddr;
75 u32 ppder;
76 u32 ppdsr;
77 u32 reserved6;
78#else
79 u32 asr;
80 u32 bsr;
81 u32 absr;
82 u32 reserved5[9];
83#endif
84 u32 ower;
85 u32 owdr;
86 u32 owsr;
87#if defined(CPU_HAS_PIO3)
88 u32 reserved7;
89 u32 aimer;
90 u32 aimdr;
91 u32 aimmr;
92 u32 reserved8;
93 u32 esr;
94 u32 lsr;
95 u32 elsr;
96 u32 reserved9;
97 u32 fellsr;
98 u32 rehlsr;
99 u32 frlhsr;
100 u32 reserved10;
101 u32 locksr;
102 u32 wpmr;
103 u32 wpsr;
104 u32 reserved11[5];
105 u32 schmitt;
106 u32 reserved12[63];
107#else
108 u32 reserved6[85];
109#endif
110} at91_port_t;
111
112typedef union at91_pio {
113 struct {
114 at91_port_t pioa;
115 at91_port_t piob;
116 at91_port_t pioc;
117 at91_port_t piod;
118 at91_port_t pioe;
119 };
120 at91_port_t port[5];
121} at91_pio_t;
122
123#ifdef CONFIG_AT91_GPIO
124int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
125int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
126#if defined(CPU_HAS_PIO3)
127int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
128int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
129int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
130int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
131int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
132#endif
133int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
134int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
135int at91_set_pio_output(unsigned port, unsigned pin, int value);
136int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
137int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
138int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
139int at91_set_pio_value(unsigned port, unsigned pin, int value);
140int at91_get_pio_value(unsigned port, unsigned pin);
141#endif
142#endif
143
144#define AT91_PIO_PORTA 0x0
145#define AT91_PIO_PORTB 0x1
146#define AT91_PIO_PORTC 0x2
147#define AT91_PIO_PORTD 0x3
148#define AT91_PIO_PORTE 0x4
149
150#endif
151