LXR uboot/arch/powerpc/cpu/mpc83xx/spl

   1/*
   2 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <mpc83xx.h>
   9
  10DECLARE_GLOBAL_DATA_PTR;
  11
  12/*
  13 * Breathe some life into the CPU...
  14 *
  15 * Set up the memory map,
  16 * initialize a bunch of registers,
  17 * initialize the UPM's
  18 */
  19void cpu_init_f (volatile immap_t * im)
  20{
  21        int i;
  22
  23        /* Pointer is writable since we allocated a register for it */
  24        gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  25
  26        /* Clear initial global data */
  27        for (i = 0; i < sizeof(gd_t); i++)
  28                ((char *)gd)[i] = 0;
  29
  30        /* system performance tweaking */
  31
  32#ifdef CONFIG_SYS_ACR_PIPE_DEP
  33        /* Arbiter pipeline depth */
  34        im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
  35                          (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
  36#endif
  37
  38#ifdef CONFIG_SYS_ACR_RPTCNT
  39        /* Arbiter repeat count */
  40        im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
  41                          (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
  42#endif
  43
  44#ifdef CONFIG_SYS_SPCR_OPT
  45        /* Optimize transactions between CSB and other devices */
  46        im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
  47                           (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
  48#endif
  49
  50        /* Enable Time Base & Decrementer (so we will have udelay()) */
  51        im->sysconf.spcr |= SPCR_TBEN;
  52
  53        /* DDR control driver register */
  54#ifdef CONFIG_SYS_DDRCDR
  55        im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
  56#endif
  57        /* Output buffer impedance register */
  58#ifdef CONFIG_SYS_OBIR
  59        im->sysconf.obir = CONFIG_SYS_OBIR;
  60#endif
  61
  62        /*
  63         * Memory Controller:
  64         */
  65
  66        /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
  67         * addresses - these have to be modified later when FLASH size
  68         * has been determined
  69         */
  70
  71#if defined(CONFIG_SYS_NAND_BR_PRELIM)  \
  72        && defined(CONFIG_SYS_NAND_OR_PRELIM) \
  73        && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
  74        && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
  75        set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
  76        set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
  77        im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
  78        im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
  79#else
  80#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
  81#endif
  82}
  83
  84/*
  85 * Get timebase clock frequency (like cpu_clk in Hz)
  86 */
  87unsigned long get_tbclk(void)
  88{
  89        return (gd->bus_clk + 3L) / 4L;
  90}
  91
  92void puts(const char *str)
  93{
  94        while (*str)
  95                putc(*str++);
  96}
  97